MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TWO SIMULTANEOUS OPERATIONS ON THE SAME ROW OF A MEMORY BANK
First Claim
1. A memory device for storing data, the memory device comprising:
- a memory bank comprising a memory array of addressable memory cells;
a pipeline configured to process read and write operations addressed to said memory bank;
an x decoder circuit coupled to said memory array for decoding an x portion of a memory address for said memory array; and
a y multiplexer circuit coupled to said memory array and operable to simultaneously multiplex across said memory array based on two y portions of memory addresses and, based thereon with said x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array, andwherein said x decoder and said y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.
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Accused Products
Abstract
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.
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Citations
17 Claims
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1. A memory device for storing data, the memory device comprising:
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a memory bank comprising a memory array of addressable memory cells; a pipeline configured to process read and write operations addressed to said memory bank; an x decoder circuit coupled to said memory array for decoding an x portion of a memory address for said memory array; and a y multiplexer circuit coupled to said memory array and operable to simultaneously multiplex across said memory array based on two y portions of memory addresses and, based thereon with said x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array, and wherein said x decoder and said y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device for storing data, the memory device comprising:
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a memory bank comprising a memory array of addressable memory cells, wherein said addressable memory cells comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells; a pipeline configured to process read and write operations addressed to said memory bank, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage; a row decoder circuit coupled to said memory array for decoding a row portion of a memory address and for asserting a row line of said memory array; and a column multiplexer circuit coupled to said memory array and operable to simultaneously multiplex based on two column portions of memory addresses and, based thereon with said row portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array, wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array. - View Dependent Claims (9, 10, 11, 12)
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13. A method of accessing a memory device, said method comprising:
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processing read and write operations addressed to a memory bank using a pipeline, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage and wherein further said memory bank comprises a memory array of addressable memory cells that comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells; decoding a row portion of a memory address and asserting a row line of said memory array using a row decoder circuit coupled to said memory array; and simultaneously multiplexing column lines of said memory array based on two column portions of memory addresses and, based thereon with said row portion, simultaneously writing a value and reading a value associated with two separate memory cells of said memory array using a column multiplexer circuit coupled to said memory array, and wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array. - View Dependent Claims (14, 15, 16, 17)
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Specification