MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEMORY DEVICE THAT USES DYNAMIC REDUNDANCY REGISTERS

• US 20180122449A1
• Filed: 12/27/2017
• Published: 05/03/2018
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies, Inc.
• Inventors: BERGER, Neal, LOUIE, Benjamin, EL-BARAJI, Mourad, CRUDELE, Lester, HILLMAN, Daniel
• Granted Patent: US 10,192,601 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods

Abstract

A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The pipeline also comprises a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank. Further, the pipeline comprises a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address.

Claims

1. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

an input register operable to receive a first data word and an associated address to be written into a memory bank;

a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register in a first clock cycle, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address; and

a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register in a second clock cycle, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address, and further wherein a second data word is input into the first write register in the second clock cycle subsequent to writing the first data word into the second write register from the first write register, wherein the second pipe-stage follows the first pipe-stage.

2. The memory pipeline of claim 1, further comprising:

a delay register of the third pipe-stage operable to receive the first data word and the associated address from the second write register on a third cycle, wherein a third data word is input into the first write register and the second data word is transferred from the first write register into the second write register for a second attempt at writing the second data word on the third cycle into the memory bank, wherein the third pipe-stage follows the second pipe-stage.

3. The memory pipeline of claim 2, wherein the delay register is further operable to provide a delay cycle between the write register and a verify register, wherein the delay cycle is used to find a verify operation in a first level dynamic redundancy register with a row address in common with the first data word.

4. The memory pipeline of claim 3, wherein the delay register is further operable to transmit the first data word and the associated address to the first level dynamic redundancy register responsive to receipt of a row address change signal.

5. The memory pipeline of claim 2, further comprising:

a verify register of the fourth pipe-stage coupled to the delay register wherein the verify register is operable to receive the first data word from the delay register on a fourth clock cycle, and wherein the verify register performs a read operation on the memory bank at the associated address to determine whether the first data word wrote correctly to the memory bank, wherein the fourth pipe-stage follows the third pipe-stage.

6. The memory pipeline of claim 5, further comprising:

compare logic operable to perform a compare operation between the first data word in the verify register and a data word read from the memory bank at the associated address in the verify register.

7. The memory pipeline of claim 6, further comprising:

a verify results register of the fifth pipe-stage operable to receive the first data word and the associated address from the verify register, wherein responsive to a determination that a verify operation associated with the compare operation failed, the verify results register is further operable to transfer the first data word and the associated address to a first level dynamic redundancy register, wherein the fifth pipe-stage follows the fourth pipe-stage.

8. The memory pipeline of claim 1, wherein memory cells of said memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

9. The memory pipeline of claim 1, wherein responsive to receiving a read operation, write operations associated with the memory pipeline are stalled until the read operation is completed.

10. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

an input register operable to receive a first data word and an associated address to be written into a memory bank;

a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register in a first part of the first clock cycle, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address; and

a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register in a second part of the first clock cycle, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address, and further wherein a second data word is input into the first write register in the second part of the first clock cycle subsequent to writing the first data word into the second write register from the first write register, wherein the second pipe-stage follows the first pipe-stage.

11. The memory pipeline of claim 10, further comprising:

a delay register of the third pipe-stage operable to receive the first data word and the associated address from the second write register on a first part of a second cycle, wherein a third data word is input into the first write register and the second data word is transferred from the first write register into the second write register for a second attempt at writing the second data word on the first part of the second cycle into the memory bank, wherein the third pipe-stage follows the second pipe-stage.

12. The memory pipeline of claim 11, wherein the delay register is further operable to provide a delay cycle between the write register and a verify register, wherein the delay cycle is used to find a verify operation in a first level dynamic redundancy register with a row address in common with the first data word.

13. The memory pipeline of claim 12, wherein the delay register is further operable to transmit the first data word and the associated address to the first level dynamic redundancy register responsive to receipt of a row address change signal.

14. The memory pipeline of claim 10, wherein memory cells of said memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

15. A system for performing a write operation in a memory device, the system comprising:

a memory pipeline;

a memory bank coupled to the memory pipeline; and

a first level dynamic redundancy register, wherein the memory pipeline comprises;

an input register operable to receive a first data word and an associated address to be written into the memory bank;

a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register in a first clock cycle, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank at a location corresponding to the associated address; and

a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register in a second clock cycle, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address, and further wherein a second data word is input into the first write register in the second clock cycle subsequent to writing the first data word into the second write register from the first write register, wherein the second pipe-stage follows the first pipe-stage.

16. The system of claim 15, further comprising:

a delay register of the third pipe-stage operable to receive the first data word and the associated address from the second write register on a third cycle, wherein a third data word is input into the first write register and the second data word is transferred from the first write register into the second write register for a second attempt at writing the second data word on the third cycle into the memory bank, wherein the third pipe-stage follows the second pipe-stage.

17. The system of claim 16, wherein the delay register is further operable to provide a delay cycle between the write register and a verify register, wherein the delay cycle is used to find a verify operation in the first level dynamic redundancy register with a row address in common with the first data word.

18. The system of claim 17, wherein the delay register is further operable to transmit the first data word and the associated address to the first level dynamic redundancy register responsive to receipt of a row address change signal.

19. The system of claim 16, further comprising:

a verify register of the fourth pipe-stage coupled to the delay register wherein the verify register is operable to receive the first data word from the delay register on a fourth clock cycle, and wherein the verify register performs a read operation on the memory bank at the associated address to determine whether the first data word wrote correctly to the memory bank, wherein the fourth pipe-stage follows the third pipe-stage.

20. The system of claim 19, further comprising:

compare logic operable to perform a compare operation between the first data word in the verify register and a data word read from the memory bank at the associated address in the verify register.

21. The system of claim 20, further comprising:

a verify results register of the fifth pipe-stage operable to receive the first data word and the associated address from the verify register, wherein responsive to a determination that a verify operation associated with the compare operation failed, the verify results register is further operable to transfer the first data word and the associated address to a first level dynamic redundancy register, wherein the fifth pipe-stage follows the fourth pipe-stage.