HALF DENSITY FERROELECTRIC MEMORY AND OPERATION

• US 20180122452A1
• Filed: 12/26/2017
• Published: 05/03/2018
• Est. Priority Date: 06/13/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Ingalls, Charles L.
• Granted Patent: US 10,360,966 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

Claims

1. A method, comprising:

selecting a first ferroelectric memory cell in electronic communication with an access line of a memory array;

selecting a second ferroelectric memory cell in electronic communication with the access line; and

determining a logic state of the first ferroelectric memory cell based at least in part on a logic state of the second ferroelectric memory cell.

2. The method of claim 1, wherein determining the logic state of the first ferroelectric memory cell comprises:

comparing the logic state of the first ferroelectric memory cell to the logic state of the second ferroelectric memory cell at a same sense component.

3. The method of claim 1, wherein the logic state of the second ferroelectric memory cell is opposite the logic state of the first ferroelectric memory cell.

4. The method of claim 1, further comprising:

activating a switch to couple the second ferroelectric memory cell with a sense component that is in electronic communication with the first ferroelectric memory cell.

5. The method of claim 1, further comprising:

applying a voltage to an isolation component to couple the first ferroelectric memory cell with a sense component.

6. The method of claim 1, further comprising:

performing a write-back operation based at least in part on determining the logic state of the first ferroelectric memory cell, wherein the write-back operation restores the logic state of the first ferroelectric memory cell and the logic state of the second ferroelectric memory cell.

7. The method of claim 1, further comprising:

receiving a command to write the first ferroelectric memory cell with the logic state;

writing the first ferroelectric memory cell with the logic state in response to the command; and

writing the second ferroelectric memory cell with an opposite logic state based at least in part on receiving the command to write to the first ferroelectric memory cell.

8. An electronic memory apparatus, comprising:

a first ferroelectric memory cell in electronic communication with an access line;

a second ferroelectric memory cell in electronic communication with the access line; and

a first sense component in electronic communication with the first ferroelectric memory cell and the second ferroelectric memory cell.

9. The electronic memory apparatus of claim 8, further comprising:

a first switch between the second ferroelectric memory cell and the first sense component, wherein the second ferroelectric memory cell comprises a reference input to the first sense component for sensing operations of the first ferroelectric memory cell.

10. The electronic memory apparatus of claim 9, wherein the first switch comprises a transistor operable to couple the second ferroelectric memory cell to the first sense component based at least in part on a threshold voltage applied to the transistor.

11. The electronic memory apparatus of claim 8, further comprising:

a third ferroelectric memory cell in electronic communication with the first sense component;

a fourth ferroelectric memory cell in electronic communication with the first sense component; and

a second switch between the fourth ferroelectric memory cell and the first sense component, wherein the fourth ferroelectric memory cell comprises a reference input to the first sense component for sensing operations of the third ferroelectric memory cell.

12. The electronic memory apparatus of claim 11, further comprising:

a first isolation device between the first ferroelectric memory cell and the first sense component;

a first activation line in electronic communication with the first isolation device;

a second sense component in electronic communication with the second ferroelectric memory cell;

a second isolation device between the second ferroelectric memory cell and the second sense component; and

a second activation line in electronic communication with the second isolation device.

13. The electronic memory apparatus of claim 12, further comprising:

a third isolation device between the third ferroelectric memory cell and the first sense component;

a third activation line in electronic communication with the third isolation device;

a fourth isolation device between the fourth ferroelectric memory cell and the second sense component; and

a fourth activation line in electronic communication with the fourth isolation device.

14. An electronic memory apparatus, comprising:

a first ferroelectric memory cell in electronic communication with an access line;

a second ferroelectric memory cell in electronic communication with the access line; and

a first sense component in electronic communication with the first ferroelectric memory cell and the second ferroelectric memory cell; and

a controller in electronic communication with the first sense component, the first and second ferroelectric memory cells, and the access line, wherein the controller is operable to;

select the first ferroelectric memory cell in electronic communication with the access line of a memory array;

select the second ferroelectric memory cell in electronic communication with the access line; and

determine a logic state of the first ferroelectric memory cell based at least in part on a logic state of the second ferroelectric memory cell.

15. The electronic memory apparatus of claim 14, wherein the controller is operable to:

comparing the logic state of the first ferroelectric memory cell to the logic state of the second ferroelectric memory cell at a same sense component.

16. The electronic memory apparatus of claim 14, wherein the logic state of the second ferroelectric memory cell is opposite the logic state of the first ferroelectric memory cell.

17. The electronic memory apparatus of claim 14, wherein the controller is operable to:

compare the logic state of the first ferroelectric memory cell to the logic state of the second ferroelectric memory cell at a same sense component.

18. The electronic memory apparatus of claim 14, wherein the controller is operable to:

activate a switch to couple the second ferroelectric memory cell with a sense component that is in electronic communication with the first ferroelectric memory cell.

19. The electronic memory apparatus of claim 14, wherein the controller is operable to:

apply a voltage to an isolation component to couple the first ferroelectric memory cell with a sense component.

20. The electronic memory apparatus of claim 14, wherein the controller is operable to:

perform a write-back operation based at least in part on determining the logic state of the first ferroelectric memory cell, wherein the write-back operation restores the logic state of the first ferroelectric memory cell and the logic state of the second ferroelectric memory cell.