METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

• US 20180122463A1
• Filed: 09/21/2017
• Published: 05/03/2018
• Est. Priority Date: 10/27/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Bhavnagarwala, Azeez Jennudin, Agarwal, Piyush, Kumar, Akshay
• Granted Patent: US 10,062,435 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods

Abstract

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.

Claims

1. A device comprising:

a circuit to generate a reference current;

a circuit to generate a read voltage to be applied to terminals of a correlated electron switch (CES) element in a read operation, the CES element being capable of being placed in a high impedance or insulative state responsive to application of a programming signal to the terminals of the CES element having a critical voltage magnitude and imparting a critical current density magnitude in the CES element;

a circuit to combine a signal current from a bitline coupled to the CES element with the reference current at a node;

a circuit to detect an impedance state of the CES element during the read operation based, at least in part, on a net charge at the node; and

one or more conductive elements configured to limit a current density in the CES element during the read operation to enable a magnitude of the read voltage to equal or exceed the critical voltage magnitude while inhibiting a transition of the CES element from a low impedance or conductive state to the high impedance or insulative state.

4. The device of claim 1, and wherein the circuit to generate the reference current further comprises a circuit to source charge to the bitline in a pre-charge phase.

5. The device of claim 1, and wherein the circuit to generate the reference current further comprises a circuit to sink charge from the bitline in a pre-charge phase.

6. The device of claim 1, and wherein the circuit to generate the reference current further comprises:

a circuit to source charge to the bitline in a pre-charge phase for a first read operation; and

a circuit to sink charge from the bitline in a pre-charge phase for a second read operation.

7. The device of claim 6, wherein a current in the non-volatile memory element in the first read operation comprises a first polarity and a current in the non-volatile memory element in the second read operation comprises a second polarity opposite the first polarity.

8. The device of claim 1, and wherein the device further comprises:

first and second cross-coupled transistors having a state responsive to a difference between the reference current and a current on the bitline; and

an output circuit to provide an output signal responsive to the state of the first and second cross-coupled transistors.

9. The device of claim 1, and further comprising one or more conductive elements to limit the signal current during read operations.

10. The device of claim 1, wherein the circuit to detect the impedance state of the non-volatile memory element further comprises one or more conducting elements to selectively couple the bitline to a source voltage in response to the signal current exceeding the reference current and selectively disconnect the bitline from the source voltage in response to the signal current not exceeding the reference current.

11. The device of claim 1, wherein the circuit to detect the impedance state of the non-volatile memory element further comprises one or more conducting elements to selectively couple the bitline to a voltage supply in response to the signal current not exceeding the reference current and selectively disconnect the bitline from the voltage supply in response to the signal current exceeding the reference current.

2. (canceled)

3. (canceled)

12. A method comprising:

generating a reference current;

applying a read voltage to terminals of a correlated electron switch (CES) element, the CES element being capable of being placed in a high impedance or insulative state responsive to application of a programming signal to the terminals of the CES element having a critical voltage magnitude and imparting a critical current density magnitude in the CES element;

combining, during application of the read voltage to the terminals of the CES element, a signal current from a bitline coupled to the CES element with the reference current at a node;

limiting a current density in the CES element during application of the read voltage to the terminals of the CES element to enable a magnitude of the read voltage to equal or exceed the critical voltage magnitude while inhibiting a transition of the CES element from a low impedance or conductive state to the high impedance or insulative state; and

detecting an impedance state of the non-volatile memory element based, at least in part, on a net charge at the node.

13. The method of claim 12, and further comprising sourcing charge to the bitline in a pre-charge phase of a read operation.

14. The method of claim 12, and further comprising sinking charge from the bitline in a pre-charge phase of a read operation.

15. The device of claim 12, and further comprising:

sourcing charge to the bitline in a pre-charge phase for a first read operation; and

sinking charge from the bitline in a pre-charge phase for a second read operation.

17. The method of claim 12, wherein the non-volatile memory element comprises a correlated electron random access memory (CeRAM) element.

18. The method of claim 12, and further comprising:

limiting the signal current during read operations.

19. The method of claim 12, wherein detecting the impedance state of the non-volatile memory element further comprises:

detecting a net positive or negative current at the node.

16. (canceled)