SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY
6 Assignments
0 Petitions
Accused Products
Abstract
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can he configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.
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Citations
24 Claims
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1. (canceled)
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2. A memory array, comprising:
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multiple strings of vertically arranged memory cells, each memory cell including a respective charge storage device, each memory cell string extending between a source and a respective bit line of multiple bit lines, wherein each bit line extends in a first direction; a first group of memory cell strings each selectively coupled to a first bit line through a respective select device in each memory cell string; a second group of memory cell strings each selectively coupled to a second bit line through a respective select device in each memory cell string, wherein the second bit line is stacked above the first bit line, and wherein the first and second groups of memory cell strings are interleaved with one another in a second direction orthogonal to the first direction in which the first and second bit lines extend; access lines coupled to respective memory cells in each of the first and second groups of memory cell strings, each access line configured to allow access to a respective memory cell in each of the first and second groups of memory cell strings to perform a memory operation involving such memory cell; a memory controller configured to couple the first bit line to a shield potential during at least a portion of a memory operation involving a memory cell in a memory cell string coupled to the second bit line. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating a memory array having multiple strings of memory cells, each string having multiple charge storage devices and extending between a source and a bit line, comprising:
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applying a pass voltage to unselected access lines of multiple access lines coupled to respective memory cells in multiple strings of memory cells; applying an operational voltage to a selected access line of the multiple access lines to enable particular memory cells in multiple strings of memory cells; coupling a first bit line of multiple bit stacked bit lines to a shield voltage line during at least a portion of a memory operation, wherein a second bit line extends in a tier above the first bit line; wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second bit line during the memory operation, and wherein strings of memory cells that do not contain the enabled memory cells are operably coupled to the first bit line during at least a portion of the memory operation. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of operating a memory array having multiple strings of memory cells,
wherein each memory cell string includes multiple charge storage devices and extends between a source and a bit line, and wherein each memory cell string is coupled to a different bit line than each adjacent memory cell string, the method comprising: -
applying a read voltage to a selected access line of multiple access lines, each access line coupled to a respective memory cell in each string of a first group of strings of memory cells; applying a read pass voltage to unselected access lines of the multiple access lines; applying a pre-charge voltage to a first group of bit lines during a memory operation; applying a shield voltage to a second group of bit lines during at least a portion of the memory operation; and applying an enable voltage to select gate drain transistors of a second group of memory cell strings comprising the enabled memory cells to couple the second group of memory cell strings to respective bit lines of the second group of bit lines during the memory operation. - View Dependent Claims (22, 23, 24)
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Specification