MEMORY DEVICE AND CLOCK TRAINING METHOD THEREOF

• US 20180122486A1
• Filed: 09/11/2017
• Published: 05/03/2018
• Est. Priority Date: 10/27/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Yeonkyu, Shin, Seungjun
• Granted Patent: US 10,304,547 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.

Claims

1. A training method comprising:

providing, at a memory controller, a clock signal to a memory device to synchronize a control signal at a reference time point of the clock signal, in which the clock signal does not transition after the reference time point; and

finding a failure time point at which the memory device fails to sample the control signal at the reference time point of the clock signal, based on the clock signal and the control signal.

2. The training method of claim 1, further comprising:

setting, at the memory controller, a synchronization time point of the control signal, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point.

3. The training method of claim 2, wherein the finding of the failure time point is based on the control signal being sequentially delayed to be iteratively provided to the memory device.

4. The training method of claim 3, wherein the setting of the synchronization time point is set to a time point that is advanced from the failure time point by half a period of the clock signal, and

wherein a sampler of the memory device samples the control signal at one edge of a rising edge and a falling edge of the clock signal and the reference time point comprises the one edge.

5. The training method of claim 3, wherein the setting of the synchronization time point of the control signal is set to a time point that is advanced from the failure time point by a quarter of a period of the clock signal,

wherein a sampler of the memory device samples the control signal at a rising edge and a falling edge of the clock signal, respectively, and the reference time point comprises the rising edge and the falling edge of the clock signal, and

wherein the memory controller iteratively performs the providing of the clock signal, the finding of the failure time point, and the setting of the synchronization time point of the control signal on the rising edge and the falling edge of the clock signal.

6. The training method of claim 2, wherein the finding of the failure time point is based on the control signal being sequentially advanced to be iteratively provided to the memory device.

7. The training method of claim 6, wherein the setting of the synchronization time point of the control signal is set to a time point that is delayed from the failure time point by half a period of the clock signal, and

wherein a sampler of the memory device samples the control signal at one edge of a rising edge and a falling edge of the clock signal and the reference time point comprises the one edge.

8. The training method of claim 6, wherein the setting of the synchronization time point of the control signal is set to a time point that is delayed from the failure time point by a quarter of a period of the clock signal,

wherein the memory device samples the control signal at a rising edge and a falling edge of the clock signal, respectively, and the reference time point comprises the rising edge and the falling edge of the clock signal, and

wherein the memory controller iteratively performs the providing, the finding, and the setting on the rising edge and the falling edge of the clock signal.

9. The training method of claim 1, further comprising:

generating, at a memory controller, the clock signal.

10. A memory device comprising:

a latch including an input buffer configured to receive a control signal from a host; and

a sampler configured to sample the control signal provided from the input buffer in synchronization with a clock signal provided from the host;

wherein in response to executing a training operation on the memory device that includes synchronization of the control signal at a reference time point of the clock signal, and wherein the clock signal does not transition after the reference time point, the training operation is executed based on a failure time point at which the sampler fails to sample the control signal at the reference time point.

11. The memory device of claim 10, wherein the sampler samples the control signal at one edge of a rising edge and a falling edge of the clock signal and the reference time point comprises the one edge.

12. The memory device of claim 11, wherein when the training operation is executed, the control signal is sequentially delayed to be iteratively provided to the sampler, and a synchronization time point of the control signal is set to a time point that is advanced from a sampling failure time point of a delayed control signal provided by half a period of the clock signal.

13. The memory device of claim 11, wherein when the training operation is executed, the control signal is sequentially advanced to be iteratively provided to the sampler, and a synchronization time point of the control signal is set to a time point that is delayed from a sampling failure time point of an advanced control signal provided by half a period of the clock signal.

14. The memory device of claim 10, wherein the sampler samples the control signal at a rising edge and a falling edge of the clock signal, respectively, and the reference time point comprises the rising edge and the falling edge of the clock signal.

15. The memory device of claim 13, wherein when the training operation is executed, the control signal is sequentially delayed to be iteratively provided to the sampler, and a synchronization time point of the control signal is set to a time point that is advanced from a sampling failure time point of a delayed control signal provided by a quarter of a period of the clock signal, and

wherein the training is iteratively performed on the rising edge and the falling edge of the clock signal.

16. The memory device of claim 14, wherein when the training operation is executed, the control signal is sequentially advanced to be iteratively provided to the sampler, and a synchronization time point of the control signal is set to a time point that is advanced from a sampling failure time point of an advanced control signal provided by a quarter of a period of the clock signal, and

wherein the training is iteratively performed on the rising edge and the falling edge of the clock signal.

17. A memory device comprising:

a clock buffer configured to receive a clock signal from a host, wherein the clock signal does not transition after a reference time point;

an input buffer configured to receive a control signal from the host;

a sampler configured to sample the control signal provided from the input buffer in synchronization with the reference time point of the clock signal; and

a command address latch that receives a command signal and an address signal from the host;

a memory cell array in communication with the sampler and the command address latch, the memory cell array configured to store training data;

wherein the control signal is synchronized with the clock signal in response to a control signal training operation initiated by the host; and

wherein the command signal is synchronized with the clock signal in response to a command signal training operation initiated by the host.

18. The memory device according to claim 17, wherein the control signal is synchronized at an edge of the clock signal.

19. The memory device according to claim 17, wherein the command signal is synchronized at an edge of the clock signal.

20. The memory device of claim 17, further comprising:

a sense amplifier that reads the training data in the memory cell array, and

a driver that receives the training data from the sense amplifier and outputs the training data to the host.