BULB-SHAPED MEMORY STACK STRUCTURES FOR DIRECT SOURCE CONTACT IN THREE-DIMENSIONAL MEMORY DEVICE

• US 20180122904A1
• Filed: 03/14/2017
• Published: 05/03/2018
• Est. Priority Date: 11/03/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Matsumoto, Kazuyo, Kasagi, Yasuo, Shimizu, Satoshi, Ogawa, Hiroyuki, Masamori, Yohei, Yu, Jixin, Zhang, Tong, Kai, James
• Granted Patent: US 9,985,098 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

Claims

1. A three-dimensional memory device comprising:

a source semiconductor layer located over a substrate;

an etch stop semiconductor rail located in a trench in the source semiconductor layer;

a laterally alternating stack of source strap rails and dielectric rails located over the source semiconductor layer and the etch stop semiconductor rail and having a different composition than the etch stop semiconductor rail, wherein each of the source strap rails and the dielectric rails laterally extends along a first horizontal direction, the etch stop semiconductor rail laterally extends along a second horizontal direction, and the source strap rails straddle the etch stop semiconductor rail;

a vertically alternating stack of electrically conductive layers and insulating layers located over the laterally alternating stack of the source strap rails and the dielectric rails; and

an array of memory stack structures that extend through the vertically alternating stack and into an upper portion of the source semiconductor layer, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel and including an opening through which a respective one of the source strap rails contacts the semiconductor channel.

2. The three-dimensional memory device of claim 1, further comprising a diffusion barrier dielectric liner including vertical portions that laterally separate the etch stop semiconductor rail from the source semiconductor layer and a horizontal portion that underlies the etch stop semiconductor rail.

3. The three-dimensional memory device of claim 2, wherein a bottom surface of the diffusion barrier dielectric liner is within a same horizontal plane as a bottom surface of the source semiconductor layer.

4. The three-dimensional memory device of claim 1, wherein:

the source semiconductor layer comprises a first n-doped semiconductor material;

the source strap rails comprise a second n-doped semiconductor material; and

the etch stop semiconductor rail comprises a p-doped semiconductor material.

5. The three-dimensional memory device of claim 1, further comprising:

a backside trench vertically extending through the vertically alternating stack, overlying the etch stop semiconductor rail, and laterally extending along the second horizontal direction; and

an insulating wall structure located within the backside trench.

6. The three-dimensional memory device of claim 5, wherein the source strap rails contacts a recessed horizontal surface of the etch stop semiconductor rail.

7. The three-dimensional memory device of claim 1, further comprising:

a patterned dielectric liner overlying the dielectric rails; and

a cap semiconductor layer overlying the patterned dielectric liner, underlying the vertically alternating stack, and contacting top surfaces of the source strap rails.

8. The three-dimensional memory device of claim 1, wherein:

a lower portion of each memory stack structure has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure that adjoins a top end of the bulging portion; and

source strap rails contact semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure.

9. The three-dimensional memory device of claim 8, further comprising a cap semiconductor layer overlying the laterally alternating stack and underlying the vertically alternating stack, wherein a top surface of the bulging portion is within a same horizontal plane as a top surface of the cap semiconductor layer.

10. The three-dimensional memory device of claim 1, wherein each of the memory stack structures is located within a respective memory opening having a monotonically increasing lateral extent as a function of a vertical distance from the substrate between a bottommost surface of a respective memory stack structure and a bottommost electrically conductive layer within the vertically alternating stack.

11. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

12. A method of forming a three-dimensional memory device, comprising:

forming a source semiconductor layer over a substrate;

forming a line trench through the source conductive layer;

forming a etch stop semiconductor rail within the line trench;

forming a laterally alternating stack of dielectric rails and sacrificial semiconductor rails over the source conductive layer and the etch stop semiconductor rail;

forming a vertically alternating stack of insulating layers and spacer material layers over the laterally alternating stack, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

forming memory stack structures through the vertically alternating stack and the laterally alternating stack, each memory stack structure including a semiconductor channel and a memory film laterally surrounding the semiconductor channel;

forming a backside trench through the vertically alternating stack and the laterally alternating stack by an anisotropic etch process that employs the etch stop semiconductor rail as an etch stop structure;

forming source cavities by removing the sacrificial semiconductor rails and portions of each memory film adjacent to the sacrificial semiconductor rails; and

forming source strap rails in the source cavities and directly on sidewalls of the semiconductor channels.

13. The method of claim 12, further comprising forming a diffusion barrier dielectric liner in the line trench, wherein the etch stop semiconductor rail is formed within the diffusion barrier dielectric liner.

14. The method of claim 12, wherein:

the line trench extends through an entire thickness of the source semiconductor layer;

the etch stop semiconductor rail is formed by deposition and planarization of a doped semiconductor material; and

a top surface of the etch stop semiconductor rail is within a same horizontal plane as a top surface of the source semiconductor layer.

15. The method of claim 12, wherein:

the source semiconductor layer comprises a first n-doped semiconductor material;

the source strap rails comprise a second n-doped semiconductor material; and

the etch stop semiconductor rail comprises a p-doped semiconductor material.

16. The method of claim 12, wherein:

each of the dielectric rails and the sacrificial semiconductor rails laterally extend along a first horizontal direction;

the etch stop semiconductor rail extends along a second horizontal direction that is different from the first horizontal direction.

17. The method of claim 12, further comprising forming an insulating wall structure within the backside trench after formation of the source strap rails.

18. The method of claim 12, further comprising:

forming a dielectric liner over the laterally alternating stack; and

forming a cap semiconductor layer over the dielectric liner,

wherein;

the vertically alternating stack is formed over the cap semiconductor layer;

portions of the dielectric liner overlying the sacrificial semiconductor rails is removed after removal of the sacrificial semiconductor rails; and

the source strap rails are formed on a bottom surface of the cap semiconductor layer.

19. The method of claim 12, further comprising:

forming source-level memory openings within the laterally alternating stack of the dielectric rails and the sacrificial semiconductor rails;

forming sacrificial semiconductor pedestals within the source-level memory openings; and

forming memory openings through the vertically alternating stack by etching through the vertically alternating stack and by removing the sacrificial semiconductor pedestals, wherein each of the memory openings includes a volume of a respective one of the sacrificial semiconductor pedestals,

wherein memory stack structures are formed in the memory openings.

20. The method of claim 19, wherein:

a lower portion of each memory stack structure including a volume of a respective sacrificial semiconductor pedestal has a bulging portion that has a greater lateral dimension than an overlying portion of the respective memory stack structure that adjoins a top end of the bulging portion; and

the source strap rails contact the semiconductor channels of the memory stack structures at a level of the bulging portion of each memory stack structure.

21. The method of claim 12, further comprising forming memory openings through the vertically alternating stack and the laterally alternating stack,

wherein:

surfaces of each memory opening include a sidewall of a respective sacrificial semiconductor rail and a sidewall of a respective dielectric rail; and

each memory opening has a monotonically increasing lateral extent as a function of a vertical distance from the substrate between a bottommost surface of a respective memory opening and a bottommost spacer material layer within the vertically alternating stack.