INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES

• US 20180122913A1
• Filed: 10/31/2016
• Published: 05/03/2018
• Est. Priority Date: 10/31/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cheng, Kangguo, Yamashita, Tenko, Yeh, Chun-chen
• Granted Patent: US 10,439,031 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.

Claims

1. A structure comprising:

a vertical-transport field-effect transistor including a fin, a gate structure overlapping a portion of the fin that functions as a channel, a first source/drain region, and a second source/drain region, the gate structure arranged in a vertical direction between the first source/drain region and the second source/drain region; and

a vertical electrical fuse including a fuse link, a first electrode, and a second electrode connected by the fuse link with the first electrode, the fuse link arranged in the vertical direction between the first electrode and the second electrode,

wherein the first source/drain region is included in a first region of a doped semiconductor layer and the first electrode is included in a second region of the doped semiconductor layer.

2. The structure of claim 1 wherein the fuse link of the vertical electrical fuse includes a pillar comprised of a semiconductor material and a first section of an electrically-conductive layer located on an exterior surface of the pillar.

3. The structure of claim 2 wherein a second section of the electrically-conductive layer is located on the first electrode, a third section of the electrically-conductive layer is located on the second electrode, and the first section, the second section, and the third section of the electrically-conductive layer are electrically continuous.

4. The structure of claim 2 wherein the electrically-conductive layer is comprised of a silicide.

5. The structure of claim 2 wherein the electrically-conductive layer is comprised of a material having a higher electrical conductivity than the semiconductor material of the pillar.

6. The structure of claim 1 wherein the fuse link includes a nanowire comprised of a semiconductor material.

7. The structure of claim 1 wherein the pillar is smaller in cross-sectional area than the fin in a plane normal to the vertical direction.

8. The structure of claim 1 wherein the first electrode is a cathode of the vertical electrical fuse, and the second electrode is an anode of the vertical electrical fuse.

9. The structure of claim 1 further comprising:

a trench isolation region between the first region of the doped semiconductor layer and the second region of the doped semiconductor layer.

10. A method comprising:

forming a doped semiconductor layer with a first region that includes a first electrode of a vertical electrical fuse and a second region that includes a first source/drain region of a vertical-transport field effect transistor;

forming a fin on the first region of the doped semiconductor layer;

forming a fuse link on the second region of the doped semiconductor layer;

forming a gate structure that overlaps a portion of the fin that functions as a channel;

forming a second source/drain region coupled with the fin; and

forming a second electrode of the vertical electrical fuse,

wherein the gate structure is arranged in a vertical direction between the first source/drain region and the second source/drain region, and the fuse link is arranged in the vertical direction between the first electrode and the second electrode.

11. The method of claim 10 wherein the fuse link of the vertical electrical fuse includes a pillar comprised of a semiconductor material, further comprising:

forming a first section of a first electrically-conductive layer on an exterior surface of the pillar.

12. The method of claim 11 further comprising:

forming a first section of a second electrically-conductive layer on the first source/drain region; and

forming a second section of the second electrically-conductive layer on the second source/drain region,

wherein the first electrically-conductive layer and the second electrically-conductive layer are concurrently formed.

13. The method of claim 12 further comprising:

forming a second section of the first electrically-conductive layer on the first electrode; and

forming a trench isolation region in the doped semiconductor layer that is located between the second section of the first electrically-conductive layer and the first section of the second electrically-conductive layer.

14. The method of claim 11 further comprising:

forming a second section of the first electrically-conductive layer on the first electrode; and

forming a third section of the first electrically-conductive layer on the second electrode,

wherein the first section, the second section, and the third section of the first electrically-conductive layer are electrically continuous.

15. The method of claim 11 wherein the first electrically-conductive layer is comprised of a silicide formed by a silicidation process.

16. The method of claim 11 wherein the first electrically-conductive layer is comprised of a material having a higher electrical conductivity than the semiconductor material of the pillar.

17. The method of claim 10 wherein the fuse link includes a nanowire comprised of a semiconductor material, and the nanowire and the fin are concurrently formed.

18. The method of claim 10 wherein the pillar is smaller in cross-sectional area than the fin in a plane normal to the vertical direction.

19. The method of claim 10 wherein the first electrode is a cathode of the vertical electrical fuse, and the second electrode is an anode of the vertical electrical fuse.

20. The method of claim 10 further comprising:

forming a trench isolation region in the doped semiconductor layer that is located between the first region of the doped semiconductor layer and the second region of the doped semiconductor layer.