INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND ELECTRICAL FUSES
First Claim
1. A structure comprising:
- a vertical-transport field-effect transistor including a fin, a gate structure overlapping a portion of the fin that functions as a channel, a first source/drain region, and a second source/drain region, the gate structure arranged in a vertical direction between the first source/drain region and the second source/drain region; and
a vertical electrical fuse including a fuse link, a first electrode, and a second electrode connected by the fuse link with the first electrode, the fuse link arranged in the vertical direction between the first electrode and the second electrode,wherein the first source/drain region is included in a first region of a doped semiconductor layer and the first electrode is included in a second region of the doped semiconductor layer.
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Abstract
Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.
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Citations
20 Claims
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1. A structure comprising:
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a vertical-transport field-effect transistor including a fin, a gate structure overlapping a portion of the fin that functions as a channel, a first source/drain region, and a second source/drain region, the gate structure arranged in a vertical direction between the first source/drain region and the second source/drain region; and a vertical electrical fuse including a fuse link, a first electrode, and a second electrode connected by the fuse link with the first electrode, the fuse link arranged in the vertical direction between the first electrode and the second electrode, wherein the first source/drain region is included in a first region of a doped semiconductor layer and the first electrode is included in a second region of the doped semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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forming a doped semiconductor layer with a first region that includes a first electrode of a vertical electrical fuse and a second region that includes a first source/drain region of a vertical-transport field effect transistor; forming a fin on the first region of the doped semiconductor layer; forming a fuse link on the second region of the doped semiconductor layer; forming a gate structure that overlaps a portion of the fin that functions as a channel; forming a second source/drain region coupled with the fin; and forming a second electrode of the vertical electrical fuse, wherein the gate structure is arranged in a vertical direction between the first source/drain region and the second source/drain region, and the fuse link is arranged in the vertical direction between the first electrode and the second electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification