Transistors, Memory Cells and Semiconductor Constructions

• US 20180122917A1
• Filed: 12/29/2017
• Published: 05/03/2018
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Durai Vishak, Prall, Kirk D., Kinney, Wayne
• Granted Patent: US 10,943,986 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 14/0027 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10N 70/253 having three or more terminals, e.g. transistor-like devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 : Switching materials

Abstract

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Claims

1. A semiconductor construction, comprising:

a semiconductor base having a recess extending into the base through an upper surface, the base having a source region on a first side of the recess and a drain region on a second side of the recess;

a gate material disposed within the recess between the source region and the drain region;

a gate dielectric material disposed between the source region and the gate material and between the drain region and the gate material, the gate dielectric material being in direct physical contact with the semiconductor base along the source region and the drain region within the recess; and

a ferroelectric material between the first gate dielectric material and the gate material along the source region and the drain region.

2. The semiconductor construction of claim 1 wherein the ferroelectric material is in direct physical contact with the gate dielectric material.

3. The semiconductor construction of claim 1 wherein the ferroelectric material is in direct physical contact with the gate material.

4. The semiconductor construction of claim 1 wherein the gate dielectric comprises SiON.

5. The semiconductor construction of claim 1 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.

6. The semiconductor construction of claim 1 wherein the ferroelectric material comprises hafnium oxide.

7. The semiconductor construction of claim 1 wherein the gate material comprises metal.

8. The semiconductor construction of claim 1 wherein the gate dielectric material lines an entirety of the semiconductor base within the recess, along a cross section.

9. The semiconductor construction of claim 8 wherein the gate dielectric material has an outer surface contacting the semiconductor base and an opposing inner surface, and wherein the ferroelectric material is present along an entirety of the inner surface along the cross section.

10. The semiconductor construction of claim 1 wherein an entirety of the gate material is within the recess and does not extend above the upper surface.

11. A transistor, comprising:

a recessed gate;

a source region;

a drain region; and

a gate dielectric between the gate and the source and drain regions;

the gate dielectric comprising a non-ferroelectric material and a ferroelectric material between the source region and the recessed gate.

12. The transistor of claim 11 wherein the gate dielectric further comprises a non-ferroelectric material and a ferroelectric material between the drain region and the recessed gate.

13. The transistor of claim 11 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.

14. The transistor of claim 11 wherein the ferroelectric material comprises hafnium oxide.

15. The transistor of claim 11 wherein the non-ferroelectric material comprises SiON.

16. The transistor of claim 11 wherein the recessed gate is disposed within a recess in a semiconductive material and wherein the gate dielectric lines an entirety of the recess along a cross section.

17. The transistor of claim 11 wherein the gate dielectric is in direct physical contact with the semiconductive material.