FLIP-FLOP AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

• US 20180123569A1
• Filed: 06/15/2017
• Published: 05/03/2018
• Est. Priority Date: 10/31/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HWANG, HYUN-CHUL, KIM, AH-REUM, KIM, MIN-SU
• Granted Patent: US 10,651,828 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

Claims

1. A flip-flop which generates a first feedback signal using a signal generated inside the flip-flop, the flip-flop comprising:

a first stage circuit that receives a first data signal and a clock signal and that generates a first internal signal through a first node;

a second stage circuit that receives the first internal signal, the clock signal, and the first feedback signal and that generates a second internal signal through a second node; and

a third stage circuit that generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal,

wherein the second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

2. The flip-flop according to claim 1,

wherein the second stage circuit forms a second current path between the second node and the power supply, based on the first internal signal and the clock signal.

3. The flip-flop according to claim 2,

wherein the second stage circuit cuts off the at least one first current path and the second current path, such that the second node is kept discharged, when:

the second node is discharged;

the first internal signal is constant at one of the first level and the second level; and

the clock signal transits from the first level to the second level.

4. The flip-flop according to claim 3, wherein the second stage circuit forms the second current path, such that the second node is precharged by the second current path, when:

the second node is discharged;

the first internal signal is constant at the other one of the first level and the second level; and

the clock signal transits from the first level to the second level.

5. The flip-flop according to claim 1,

wherein the first feedback signal comprises a signal generated using the second internal signal.

6. The flip-flop according to claim 5,

wherein the first feedback signal further comprises a signal generated using the second data signal.

7. The flip-flop according to claim 1, wherein the second stage circuit comprises:

a pull-up circuit connecting the power supply to the second node; and

a pull-down circuit connecting a ground to the second node,

the pull-up circuit comprises;

at least one first PMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second PMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third PMOS transistor controlled to be turned on/off by receiving the first feedback signal, and

the pull-down circuit comprises;

at least one first NMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second NMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third NMOS transistor controlled to be turned on/off by receiving the first feedback signal.

8. The flip-flop according to claim 1,

wherein the second stage circuit comprises at least one switch device controlled to be turned on/off based on the first feedback signal, and cuts off the at least one first current path by turning off the switch device.

9. The flip-flop according to claim 1,

wherein the first stage circuit further receives a second feedback signal, comprises at least one switch device controlled to be turned on/off based on the second feedback signal, and controls the switch device such that the first node does not float by grounding the first node or connecting the first node to the power supply, based on the second feedback signal.

10. A flip-flop which is connected to a power supply and a ground and generates a second data signal by receiving a first data signal and a clock signal from outside of the flip-flop, the flip-flop comprising:

a first stage circuit that generates a first internal signal through a first node using the first data signal and the clock signal;

a second stage circuit that generates a second internal signal through a second node; and

a third stage circuit that generates the second data signal by latching the second internal signal using the second internal signal and the clock signal,

wherein the first stage circuit receives a first feedback signal that is generated using the first internal signal and prevents the first node from floating by grounding the first node or connecting the first node to the power supply, based on the first feedback signal.

11. The flip-flop according to claim 10, wherein the first stage circuit comprises:

an AND gate that generates a first output signal by receiving the first feedback signal and the clock signal; and

a NOR gate that generates a second output signal by receiving the first output signal and the first data signal.

12. The flip-flop according to claim 10, wherein the first stage circuit further comprises:

a first switch device that connects the first node to the power supply, based on the first feedback signal, when the first internal signal is at a first level; and

a second switch device that grounds the first node, based on the first feedback signal, when the first internal signal is at a second level.

13. The flip-flop according to claim 10,

wherein the second stage circuit receives a second feedback signal that is generated using the second internal signal;

outputs the second internal signal that is at a level corresponding to the first internal signal when levels of the first internal signal and the clock signal are the same, based on the first internal signal, the clock signal, and the second feedback signal; and

outputs the second internal signal maintaining a previous level when the levels of the first internal signal and the clock signal are different, based on the first internal signal, the clock signal, and the second feedback signal; and

outputs the second internal signal that is at a level corresponding to the first internal signal when levels of the first internal signal and the clock signal are different, based on the first internal signal, the clock signal, and the second feedback signal; and

outputs the second internal signal maintaining a previous level when the levels of the first internal signal and the clock signal are the same, based on the first internal signal, the clock signal, and the second feedback signal.

14. The flip-flop according to claim 13, wherein the second stage circuit comprises:

a third node for generating the second internal signal; and

a pull-up circuit that forms a plurality of current paths between the second node and the power supply, based on the first internal signal, the clock signal, and the second feedback signal that is generated using the second internal signal.

15. The flip-flop according to claim 14,

wherein, in order to reduce power consumption of the flip-flop, the pull-up circuit cuts off the plurality of current paths between the second node and the power supply, based on the clock signal and the second feedback signal that is generated using the second internal signal.

16. A flip-flop, the flip-flop comprising:

a first stage circuit that receives a first data signal and a clock signal and that generates a first internal signal through a first node;

a second stage circuit that receives the first internal signal and the clock signal, and that generates a second internal signal through a second node; and

a third stage circuit that generates a second data signal by latching the second internal signal using the second internal signal and the clock signal,

wherein at least one of the first stage circuit and the second stage circuit receives a feedback signal from an output of one of the first stage circuit and the second stage circuit, and

when the second stage circuit receives the feedback signal from the second stage circuit and the second data signal is generated when the clock signal is at a first level, the second stage circuit cuts off at least one first current path between the second node and a power supply, based on the feedback signal from the second stage circuit, when the clock signal is at a second level, and

when the first stage circuit receives the feedback signal from the first stage circuit, the first stage circuit grounds the first node or connects the first node to the power supply, based on the feedback signal from the first stage circuit, to prevent the first node from floating.

17. The flip-flop according to claim 16,

wherein the second stage circuit forms a second current path between the second node and the power supply, based on the first internal signal and the clock signal.

18. The flip-flop according to claim 17,

wherein the second stage circuit cuts off the at least one first current path and the second current path, such that the second node is kept discharged, when:

the second node is discharged;

the first internal signal is constant at one of the first level and the second level; and

the clock signal transits from the first level to the second level, and

wherein the second stage circuit forms the second current path, such that the second node is precharged by the second current path, when;

the second node is discharged;

the first internal signal is constant at the other one of the first level and the second level; and

the clock signal transits from the first level to the second level.

19. The flip-flop according to claim 16,

wherein the second stage circuit comprises at least one switch device controlled to be turned on/off based on the feedback signal from the second stage circuit, and cuts off the at least one first current path by turning off the switch device.

20. The flip-flop according to claim 16,

wherein the first stage circuit comprises at least one switch device controlled to be turned on/off based on the feedback signal from the first stage circuit, and controls the switch device such that the first node does not float by grounding the first node or connecting the first node to the power supply, based on the feedback signal from the first stage circuit.