DELAY LOCKED LOOP TO CANCEL OFFSET AND MEMORY DEVICE INCLUDING THE SAME

• US 20180123601A1
• Filed: 09/07/2017
• Published: 05/03/2018
• Est. Priority Date: 10/27/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEON, Juho, CHOI, Hun-Dae
• Granted Patent: US 10,320,398 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/22 using more than one loop

Abstract

A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Claims

1. A memory device comprising:

a clock delay circuit configured to transmit a reference clock to a data output circuit; and

a delay locked loop including a variable delay circuit and a clock delay replica circuit, the variable delay circuit configured to generate a first clock by delaying the reference clock, and the clock delay replica circuit configured to receive the first clock and replicate the clock delay circuit, the delay locked loop being configured to receive a second clock which is the delayed reference clock from the clock delay circuit, and adjust a delay of the clock delay replica circuit based on the second clock and a third clock output from the clock delay replica circuit.

2. The memory device of claim 1, wherein the delay locked loop comprises:

a first phase detector configured to receive the second clock and the third clock, and to detect a phase difference between the second clock and the third clock; and

a first controller configured to adjust the delay of the clock delay replica circuit based on an output from the first phase detector.

3. The memory device of claim 2, wherein the delay locked loop further comprises:

a data output replica circuit that replicates the data output circuit, and is configured to receive the third clock.

4. The memory device of claim 3, wherein the delay locked loop further comprises:

a second phase detector configured to receive the reference clock and a fourth clock and detect a phase difference between the reference clock and the fourth clock, the fourth clock being the third clock delayed by the data output replica circuit, and

a second controller configured to adjust a delay of the variable delay circuit based on an output from the second phase detector.

5. The memory device of claim 4 further comprising:

the data output circuit configured to output a data strobe synchronized with the reference clock based on a read command.

6. The memory device of claim 5, wherein the delay locked loop further comprises:

a third phase detector configured to detect a phase difference between the data strobe and the fourth clock; and

a third controller configured to adjust a delay of the data output replica circuit based on an output from the third phase detector.

7. The memory device of claim 6, wherein the first, second, and third controllers are configured to adjust the clock delay replica circuit, the variable delay circuit, and the data output replica circuit in digital manner, respectively.

8. The memory device of claim 6, wherein the first controller is configured to transmit a first locking signal to the second controller or the third controller, in response to a phase of the third clock being locked to a phase of the second clock, and

wherein the third controller is configured to transmit a second locking signal to the first controller or the second controller, in response to a phase of the fourth clock being locked to a phase of the data strobe.

9. The memory device of claim 8

wherein the second controller is configured to generate a third locking signal with reference to the first locking signal and the second locking signal in response to the phase of the fourth clock being locked to a phase of the reference clock and the data output circuit is configured to synchronize read data with the data strobe using the third locking signal.

10. A delay locked loop comprising:

a first delay circuit configured to generate a first clock by delaying a reference clock;

a second delay circuit configured to generate a second clock by delaying the first clock;

a third delay circuit configured to generate a third clock by delaying the first clock;

a first phase detector configured to detect a phase difference between the second clock and the third clock;

a second phase detector configured to detect a phase difference between the reference clock and the third clock;

a first controller configured to adjust a delay of the third delay circuit based on an output from the first phase detector; and

a second controller configured to adjust a delay of the first delay circuit based on an output from of the second phase detector.

11. The delay locked loop of claim 10, wherein the third delay circuit replicates the second delay circuit.

12. The delay locked loop of claim 10, wherein the first controller is configured to adjust the third delay circuit in a digital manner and the second controller is configured to adjust the first delay circuit in a digital manner.

13. The delay locked loop of claim 10, wherein the first controller is configured to transmit a locking signal to the second controller, in response to a phase of the third clock being locked to a phase of the second clock.

14. The delay locked loop of claim 13, wherein the second controller is configured to synchronize the second clock with the reference clock based on the locking signal.

15. The delay locked loop of claim 14, wherein the second controller is configured to output a synchronization signal after the second clock is synchronized.

16. A memory device comprising:

a variable delay circuit configured to output a first delayed clock based on a reference clock signal and a first delay code, the first delay code indicating a delay in the variable delay circuit;

a clock delay circuit configured to output a second delayed clock based on the first delayed clock;

a data output circuit configured to output a data output signal based on the second delayed clock;

a clock delay replica circuit configured to output a third delayed clock based on the first delayed clock and a second delay code, the second delay code indicating a delay in the clock delay replica circuit;

a data output replica circuit configured to output a data output replica signal based on the third delayed clock.

17. The memory device of claim 16, further comprising:

a first controller configured to output the first delay code based on a phase difference between the reference clock signal and the data replica output signal.

18. The memory device of claim 17, further comprising:

a second controller configured to output the second delay code based on a phase difference between the second delayed clock and the third delayed clock.

19. The memory device of claim 18, further comprising:

a third controller configured to output a third delay code based on a phase difference between the data output signal and the data output replica signal, the third delay code indicating a delay in the data output replica circuit,

wherein the data output replica circuit is further configured to output the data output replica circuit based on the third delayed clock.

20. The memory device of claim 19, wherein:

the first controller is further configured to output the first delay code based on a first lock signal and a second lock signal;

the second controller is further configured to,

output the first lock signal based on the phase difference between the second delayed clock and the third delayed clock, and

output the first delay code based on the second lock signal; and

the third controller is further configured to,

output the second lock signal based on the phase difference between the data output signal and the data output replica signal, and

output the third delay code based on the first lock signal.