COARSE ADJUSTMENT CELL ARRAY APPLIED TO DIGITALLY CONTROLLED OSCILLATOR AND RELATED APPARATUS

• US 20180123606A1
• Filed: 12/29/2017
• Published: 05/03/2018
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Cai, Fei, Zhou, Shenghua
• Granted Patent: US 10,644,712 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/105 Resetting the controlled oscillator when its frequency is outside a predetermined limit
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence

Abstract

The disclosure discloses a coarse adjustment cell array applied to a digitally controlled oscillator and a related apparatus. The coarse adjustment cell array applied to the digitally controlled oscillator includes X coarse adjustment cells, and each coarse adjustment cell in the coarse adjustment cell array includes a logic cell and W fine adjustment cells; and input to a logic cell of a coarse adjustment cell i in the coarse adjustment cell array includes Y coarse adjustment control bits and W fine adjustment control bits, output from the logic cell of the coarse adjustment cell i is used to control whether W fine adjustment cells in the coarse adjustment cell i work, Y is an integer greater than 1, and X and W are integers greater than 1.

Claims

1. A coarse adjustment cell array applied to a digitally controlled oscillator, the coarse adjustment cell array comprising:

X coarse adjustment cells each comprising a logic cell and W fine adjustment cells; and

at least one logic cell of a coarse adjustment cell i configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1.

2. The coarse adjustment cell array according to claim 1, wherein:

when the Y coarse adjustment control bits are a first value, the logic cell of the coarse adjustment cell i is configured to control all the W fine adjustment cells in the coarse adjustment cell i to work;

when the Y coarse adjustment control bits are a second value, the logic cell of the coarse adjustment cell i is configured to control all the W fine adjustment cells in the coarse adjustment cell i not to work; and

when the Y coarse adjustment control bits are a third value, the logic cell of the coarse adjustment cell i is configured to control, based on a value of the W fine adjustment control bits, some of the W fine adjustment cells in the coarse adjustment cell i to work, wherein the first value, the second value, and the third value are different from each other.

3. The coarse adjustment cell array according to claim 2, wherein:

there is a one-to-one correspondence between the W fine adjustment cells in the coarse adjustment cell i and the W fine adjustment control bits; and

when the Y coarse adjustment control bits are the third value, the output from the logic cell of the coarse adjustment cell i is used to control a fine adjustment cell that is in the W fine adjustment cells in the coarse adjustment cell i and that is corresponding to a fine adjustment control bit whose value is 1 to work, and control a fine adjustment cell that is in the W fine adjustment cells in the coarse adjustment cell i and that is corresponding to a fine adjustment control bit whose value is 0 not to work;

or

when the Y coarse adjustment control bits are the third value, the output from the logic cell of the coarse adjustment cell i is used to control a fine adjustment cell that is in the W fine adjustment cells in the coarse adjustment cell i and that is corresponding to a fine adjustment control bit whose value is 0 to work, and control a fine adjustment cell that is in the W fine adjustment cells in the coarse adjustment cell i and that is corresponding to a fine adjustment control bit whose value is 1 not to work.

4. The coarse adjustment cell array according to claim 1, wherein W is equal to 2ⁿ, and n is a positive integer.

5. The coarse adjustment cell array according to claim 1, wherein Y is equal to 2.

6. A digitally controlled oscillator, comprising:

a coarse adjustment cell array, comprising;

X coarse adjustment cells each comprising a logic cell and W fine adjustment cells, and

at least one logic cell of a coarse adjustment cell i configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1;

a coarse adjustment row-column decoder configured to decode an input first control signal and output A coarse adjustment control bits;

a fine adjustment row-column decoder configured to decode an input second control signal and output B fine adjustment control bits; and

wherein a set formed by the Y coarse adjustment control bits is a subset of a set comprising the A coarse adjustment control bits, and a set comprising the W fine adjustment control bits is a subset of a set comprising the B fine adjustment control bits.

7. The digitally controlled oscillator according to claim 6, wherein the set comprising the W fine adjustment control bits is equal to the set comprising the B fine adjustment control bits, and each coarse adjustment cell in the coarse adjustment cell array shares the W fine adjustment control bits.

8. The digitally controlled oscillator according to claim 6, wherein two adjacent coarse adjustment cells in the coarse adjustment cell array share one coarse adjustment control bit in the A coarse adjustment control bits, and any two adjacent coarse adjustment cells in the coarse adjustment cell array share different coarse adjustment control bits in the A coarse adjustment control bits.

9. The digitally controlled oscillator according to claim 6, wherein the coarse adjustment row-column decoder comprises:

A coarse adjustment control bit output cables, and the A coarse adjustment control bits are in a one-to-one correspondence with the A coarse adjustment control bit output cables.

10. The digitally controlled oscillator according to claim 6, wherein the fine adjustment row-column decoder comprises:

B fine adjustment control bit output cables, and the B fine adjustment control bits are in a one-to-one correspondence with the B fine adjustment control bit output cables.

11. A frequency synthesizer, comprising:

a digitally controlled oscillator, comprising;

a coarse adjustment cell array, comprising;

X coarse adjustment cells each comprising a logic cell and W fine adjustment cells; and

at least one logic cell of a coarse adjustment cell i configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1,

a coarse adjustment row-column decoder configured to decode a first control signal and output A coarse adjustment control bits,

a fine adjustment row-column decoder configured to decode a second control signal and output B fine adjustment control bits, and

wherein a set formed by the Y coarse adjustment control bits is a subset of a set comprising the A coarse adjustment control bits, and a set comprising the W fine adjustment control bits is

a subset of a set comprising the B fine adjustment control bits; and

a digital logic cell configured to output the first control signal to the coarse adjustment row-column decoder and output the second control signal to the fine adjustment row-column decoder.

12. The frequency synthesizer according to claim 11, wherein the digital logic cell is configured to:

output the first control signal to the coarse adjustment row-column decoder according to a frequency dividing control word and a reference frequency that are input to the digital logic cell; and

output the second control signal to the fine adjustment row-column decoder according to the frequency dividing control word and the reference frequency that are input to the digital logic cell.