RSA DECRYPTION PROCESSOR AND METHOD FOR CONTROLLING RSA DECRYPTION PROCESSOR
First Claim
1. An RSA decryption processor, comprising a memory, a control component, and a parallel processor, whereinthe memory is configured to store decryption parameters comprising a private key;
- the control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor; and
the parallel processor is configured to;
read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts.
3 Assignments
0 Petitions
Accused Products
Abstract
The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.
4 Citations
16 Claims
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1. An RSA decryption processor, comprising a memory, a control component, and a parallel processor, wherein
the memory is configured to store decryption parameters comprising a private key; -
the control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor; and the parallel processor is configured to;
read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and the method comprises:
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receiving a ciphertext set; and sending a decryption signal comprising the ciphertext set to the parallel processor, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. - View Dependent Claims (10, 11, 12)
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13. A non-transitory storage medium storing one or more programs, the one or more programs when executed by an apparatus, causing the apparatus to perform operations for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and the operations comprises:
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receiving a ciphertext set; and sending a decryption signal comprising the ciphertext set to the parallel processor, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. - View Dependent Claims (14, 15, 16)
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Specification