COMPUTER ARCHITECTURE

• US 20180129437A1
• Filed: 11/09/2016
• Published: 05/10/2018
• Est. Priority Date: 11/09/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Belliard, Vincent Roger Maurice
• Granted Patent: US 10,613,860 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 9/3001 Arithmetic instructions

Abstract

A tagged memory organized is into memory chunks. Each memory chunk has a data field, a type field and an owner address field. The type field indicates type of data stored in the data field. The owner address field indicates which objects own which memory chunks. A memory manager has exclusive ability to allocate the memory chunks, deallocate the memory chunks, write to the memory chunks and read the memory chunks.

Claims

1. A memory system, comprising:

a tagged memory organized into memory chunks, each memory chunk including the following fields;

a data field,

a type field, that indicates type of data stored in the data field, and

an owner address field that indicates which objects own which memory chunks, wherein a same object can own a plurality of sequential memory chunks that are sequentially organized within the tagged memory and wherein all memory chunks for single object are sequential; and

a memory manager that has exclusive ability to allocate the memory chunks, deallocate the memory chunks, write to the memory chunks and read the memory chunks.

2. A memory system as in claim 1, wherein a processing unit performs a write operation to a memory location within the tagged memory by providing to the memory manager an object address and an offset, the memory manager translating the object address and the offset into a chunk address for the memory location within the tagged memory in order to perform the write operation and instead raises an exemption.

3. A memory system as in claim 2, wherein when the chunk address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager does not perform the write operation.

4. A memory system as in claim 1, wherein a processing unit performs a read operation from a memory location within the tagged memory by providing to the memory manager an object address and an offset, the memory manager translating the object address and the offset into a chunk address for the memory location within the tagged memory in order to perform the read operation.

5. A memory system as in claim 4, wherein when the chunk address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager does not perform the read operation and instead raises an exemption.

6. A memory system as in claim 1 wherein when an object is an owner of a plurality of memory chunks, each memory chunk in the plurality of memory chunks will have a value in the owner address field that is equal to an address for the object within the tagged memory.

7. A memory system as in claim 6 wherein the address for the object within the tagged memory is an address for a first memory chunk owned by the object.

8. A computing system comprising:

a tagged memory organized into memory chunks, each memory chunk including the following fields;

a data field, and

a type field, that indicates type of data stored in the data field,

a memory manager that has exclusive ability to allocate the memory chunks, write to the memory chunks and read the memory chunks;

plurality of registers, each register having storage capacity to store a value for the data field and a value for the type field; and

a processing unit that uses the registers to execute instructions, wherein the instructions specify functions that can be performed on source arguments that include values in both the date field and the type field.

9. A computing system as in claim 8 wherein the processing unit is an arithmetic processing unit.

10. A computing system as in claim 8, wherein the processing unit performs a write operation to a memory location within the tagged memory by providing to the memory manager an object address and an offset, the memory manager translating the object address and the offset into chunk address for the memory location within the tagged memory in order to perform the write operation.

11. A computing system as in claim 8, wherein the processing unit performs a read operation from a memory location within the tagged memory by providing to the memory manager an object address and an offset, the memory manager translating the object address and the offset into a chunk address for the memory location within the tagged memory in order to perform the read operation.

12. A computing system as in claim 8 wherein when an object is an owner of a plurality of memory chunks, each memory chunk in the plurality of memory chunks will have a value in the owner address field that is equal to an address for the object within the tagged memory.

13. A computing system as in claim 8 wherein a processing unit that uses the registers to execute instructions, wherein the instructions specify functions that can be performed on source arguments of different types so that type of source argument used in execution of the instruction is determined by data type as indicated by a value in the type field of each source argument for the function.

14. A computing system as in claim 8 wherein each memory chunk additionally includes the following field:

an owner address field that indicates which objects own which memory chunks, wherein a same object can own a plurality of sequential memory chunks that are sequentially organized within the tagged memory and wherein all memory chunks for single object are sequential.

15. A computing system as in claim 8 wherein the type field of the memory can indicate whether data is an instruction.

16. A computing system as in claim 15 wherein an instruction opcode uses the data field and some bits of the type field.

17. A computing system as in claim 16 wherein the only way to generate an instruction is by using a special instruction which generates a new instruction.

18. A method for performing memory accesses within a memory system, the method comprising:

organizing a tagged memory into memory chunks, each memory chunk including the following fields;

a data field,

a type field, that indicates type of data stored in the data field,

an owner address field that indicates which objects own which memory chunks, wherein a same object can own a plurality of sequential memory chunks that are sequentially organized within the tagged memory and wherein all memory chunks for single object are sequential; and

exclusively utilizing a memory manager to allocate the memory chunks, write to the memory chunks and read the memory chunks.

19. A method as in claim 18, additionally comprising:

performing a write operation by a processing unit, including;

providing, from the processing unit to the memory manager, an object address and an offset,

translating, by the memory manager, the object address and the offset into an address for the memory location within the tagged memory,

performing, by the memory manager, the write operation to the memory location by the memory manager.

20. A method as in claim 19, wherein when the address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager does not perform the write operation and instead raises an exemption.

21. A method as in claim 18, additionally comprising:

performing a read operation by a processing unit, including;

providing, from the processing unit to the memory manager, an object address and an offset,

translating, by the memory manager, the object address and the offset into a chunk address for the memory location within the tagged memory, and

performing, by the memory manager, the read operation from the memory location by the memory manager.

22. A method as in claim 18, additionally comprising:

executing an instruction by the processor, including;

obtaining source arguments for executing the instruction from a plurality of registers, each register having storage capacity to store a value for the data field and a value for the type field.

23. A method as in claim 22, wherein executing the instruction by the processor additionally includes,

using, by the processor, data type as indicated by a value in the type field of each source argument for the function to determine type of source argument used in execution of the instruction and not using the instruction itself to determine type of source argument used in execution of the instruction.