MEMORY SYSTEM PERFORMING ERROR CORRECTION OF ADDRESS MAPPING TABLE

• US 20180129563A1
• Filed: 09/28/2017
• Published: 05/10/2018
• Est. Priority Date: 11/07/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Hyunsik, KIM, Tae-Hwan
• Granted Patent: US 10,635,530 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

Claims

1. A memory system comprising:

a nonvolatile memory device;

a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device; and

a controller configured to;

store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM;

read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data comprising a target parity and physical addresses of the nonvolatile memory device; and

perform an error correction on the read target address mapping data, using the target parity.

2. The memory system of claim 1, wherein the physical addresses of the nonvolatile memory corresponds to a target physical address chunk, and

wherein the target parity is generated based on the target physical address chunk.

3. The memory system of claim 2, wherein the target physical address chunk comprises a target physical address corresponding to the logical address.

4. The memory system of claim 1, wherein the controller is further configured to:

divide the read target address mapping data into the target parity and a target physical address chunk comprising a target physical address corresponding to the logical address; and

detecting and correcting an error of the target physical address chunk, using the target parity.

5. The memory system of claim 4, wherein the controller is further configured to:

replace, with a new physical address, the target physical address corresponding to the logical address, in the target physical address chunk of which the error is corrected, to generate a new physical address chunk;

generate a new parity, based on the generated new physical address chunk;

combine the generated new physical address chunk and the generated new parity to generate new address mapping data; and

store the generated new address mapping data in the DRAM.

6. The memory system of claim 5, wherein the controller is further configured to replace the target address mapping data in the DRAM with the generated new address mapping data.

7. The memory system of claim 1, wherein a capacity of the address mapping table is proportional to a capacity of the nonvolatile memory device.

8. A memory system comprising:

a nonvolatile memory device;

a DRAM configured to store an address mapping table for an access to the nonvolatile memory device; and

a controller configured to;

store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM; and

access the nonvolatile memory device by performing an error detection and correction on target address mapping data corresponding to the access, among the stored address mapping table, the target address mapping data comprising physical addresses of the nonvolatile memory device and a target parity corresponding to the physical addresses.

9. The memory system of claim 8, wherein the controller comprises a mapping table error correction circuit connected to the DRAM and configured to perform the error detection and correction on the target address mapping data.

10. The memory system of claim 9, wherein the mapping table error correction circuit comprises a mapping table error correction decoder configured to:

divide the target address mapping data into a target physical address chunk and the target parity; and

detect and correct an error of the target physical address chunk, using the target parity.

11. The memory system of claim 10, wherein the mapping table error correction circuit further comprises an address processor configured to obtain a target physical address corresponding to the access, from the target physical address chunk.

12. The memory system of claim 10, wherein the mapping table error correction circuit comprises an address processor configured to replace, with a new physical address, a target physical address corresponding to the access, in the target physical address chunk of which the error is corrected, to generate a new physical address chunk.

13. The memory system of claim 12, wherein the mapping table error correction circuit further comprises a mapping table error correction encoder configured to:

generate a new parity, based on the generated new physical address chunk; and

combine the generated new physical address chunk and the generated new parity to generate new address mapping data.

14. The memory system of claim 13, wherein the mapping table error correction encoder is further configured to replace the target address mapping data in the DRAM with the generated new address mapping data to store the generated new address mapping data in the DRAM.

15. The memory system of claim 9, wherein the mapping table error correction circuit is further configured to perform the error detection and correction on the target address mapping data through one read operation from the DRAM.

16. The memory system of claim 8, wherein the memory system comprises a solid state drive or a universal flash storage.

17. A method of controlling a memory system comprising a nonvolatile memory device and a dynamic random access memory (DRAM), the method comprising:

receiving, from a host, a request to translate a logical address that is used by the host to a target physical address of the nonvolatile memory device;

reading target address mapping data corresponding to the logical address of the received request, from pieces of address mapping data that are stored in the DRAM, the target address mapping data comprising a target parity and target physical addresses of the nonvolatile memory device;

correcting an error of the target physical addresses included in the read target address mapping data, using the target parity; and

outputting the target physical address corresponding to the logical address, among the target physical addresses of which the error is corrected.

18. The method of claim 17, wherein each of the pieces of the address mapping data has a size of a burst length of the DRAM.

19. The method of claim 17, wherein the request received from the host comprises a new physical address corresponding to the logical address, for a write operation, and

the method further comprises:

replacing, with the new physical address of the received request, the target physical address corresponding to the logical address, among the target physical addresses of which the error is corrected, to generate new physical addresses of the nonvolatile memory device;

generating a new parity, based on the generated new physical addresses;

combining the generated new physical addresses and the generated new parity to generate new address mapping data; and

replacing the target address mapping data in the DRAM with the generated new address mapping data to store the generated new address mapping data in the DRAM.

20. The method of claim 17, wherein the correcting is performed through one read operation from the DRAM.