STAIR STEP FORMATION USING AT LEAST TWO MASKS

• US 20180130700A1
• Filed: 01/10/2018
• Published: 05/10/2018
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ha, Chang Wan, Wolstenholme, Graham R., Thimmegowda, Deepak
• Granted Patent: US 10,269,626 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76822 Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Claims

1-20. -20. (canceled)

21. An apparatus, comprising:

horizontal conductive lines coupled to a non-linear string of memory cells, the horizontal conductive lines formed from a stack of alternating conductive materials and insulating materials having a stair step structure at an edge of the stack.

22. The apparatus of claim 21, wherein at least a first portion of the non-linear string of memory cells are oriented vertically and at least a second portion of the non-linear string of memory cells are not oriented vertically.

23. The apparatus of claim 21, wherein the non-linear string of memory cells is substantially U-shaped.

24. The apparatus of claim 21, wherein the string of memory cells comprises a three-dimensional NAND string.

25. The apparatus of claim 21, further comprising a string driver coupled to the conductive lines and respective steps of the stair step structure.

26. The apparatus of claim 21, wherein stair steps of the stair step structure each include at least one of the conductive material and the insulating material.

27. The apparatus of claim 21, wherein at least a portion of the stack is devoid of the stair step structure.

28. An apparatus, comprising:

horizontal conductive lines coupled to a linear string of memory cells, the horizontal conductive lines formed from a stack of alternating conductive materials and insulating materials having a stair step structure at an edge of the stack.

29. The apparatus of claim 28, wherein the linear string of memory cells are oriented vertically.

30. The apparatus of claim 28, further comprising a string driver coupled to the conductive lines and respective steps of the stair step structure.

31. The apparatus of claim 28, wherein the string of memory cells comprises a drain select gate arranged at a first end of the string of memory cells and a source select gate arranged at a second end of the string of memory cells.

32. The apparatus of claim 28, wherein the string of memory cells includes a plurality of memory cells coupled in series via a respective drain to a respective source of a plurality of select gate transistors.

33. The apparatus of claim 28, wherein at least a portion of the stack is devoid of the stair step structure.

34. A method, comprising:

forming a plurality of conductive lines comprising a stack of alternating conductive materials and insulating materials; and

forming a plurality of strings of memory cells coupled to respective conductive lines of the plurality of conductive lines, wherein

the stack of alternating conductive materials and insulating materials have a stair step structure formed at an edge of the stack.

35. The method of claim 34, wherein forming the plurality of strings of memory cells comprises forming a plurality of non-linear strings of memory cells.

36. The method of claim 35, wherein forming the plurality of non-linear strings of memory cells comprises forming a plurality of U-shaped strings of memory cells.

37. The method of claim 34, wherein forming the plurality of strings of memory cells comprises forming a plurality of linear strings of memory cells.

38. The method of claim 37, wherein forming the plurality of linear strings of memory cells comprises forming the plurality of linear memory cells such that they are arranged substantially orthogonal to the plurality of conductive lines.

39. The method of claim 34, further comprising forming a first mask over a conductive material to define a first exposed area;

and

forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area.

40. The method of claim 34, wherein the second mask is formed of a material that has an etching rate greater than that of the first mask.