Substrate Based Fan-Out Wafer Level Packaging

• US 20180130768A1
• Filed: 01/05/2017
• Published: 05/10/2018
• Est. Priority Date: 11/09/2016
• Status: Abandoned Application

• Current Assignee: Unisem Berhad (Tianshui Huatian Technology Company Limited)
• Original Assignee: Unisem Berhad (Tianshui Huatian Technology Company Limited)
• Inventors: Tan, Kim Heng, Chai, Chan Wah, Wong, Kwai Hong
• Application Number:
  US15/399,525
• Publication Number:
  US 20180130768A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Claims

1. A method for manufacturing substrate based fan-out wafer level packaging, comprising:

providing a substrate;

applying a first photoresist pattern;

depositing copper or a copper alloy on said first photoresist pattern;

applying a second photoresist pattern;

forming chip attach site pillars by depositing a layer of copper or copper alloy on said second photoresist pattern;

attaching a semiconductor device via a flip chip bonding, the attaching including;

forming a plurality of interconnect bumps between the semiconductor device and the chip attach site; and

forming a space between the semiconductor device and the substrate;

encapsulating the semiconductor device with a protective layer;

thinning a second side of the substrate, the thinning including copper etching and thinning;

applying a ball grid array pattern on the second side, the ball grid array pattern including a stress relief pattern, the stress relief pattern implemented on the ball grid array pattern and forming a relief of stress for the packaging;

etching the second side with copper;

applying a solder mask coating;

attaching a plurality of ball drops; and

singulating a unit.

2. The method of claim 1 wherein the substrate includes copper and a protective layer.

3. The method of claim 1 wherein the first pattern comprises a plurality of lands and channels.

4. The method of claim 3 wherein the first pattern is applied to a first side, the method further comprising:

coating the first side with a chemical resist to form a plurality of lands; and

exposing the first to etchant to form channels.

14. The method of claim 1 wherein the stress relief pattern is formed in a spiral pattern.

15. The method of claim 1 wherein the stress relief pattern is formed in a star burst pattern.

16. The method of claim 1 wherein the stress relief pattern is formed in a cartesian pattern.

17. The method of claim 1 wherein the stress relief pattern is formed in a star pattern.

5. (canceled)

6. (canceled)

7. A substrate based fan-out wafer level packaging, comprising:

a substrate;

a first photoresist pattern, the first photoresist pattern adapted to be applied to the substrate;

a copper or copper alloy layer, the copper or copper alloy layer adapted to be applied on top of the first photoresist pattern;

a second photoresist pattern, the second photoresist pattern adapted to be applied above the copper or copper alloy layer;

a plurality of chip attach site pillars, the chip attach site pillars including a plurality of interconnect bumps and formed on top of said second photoresist pattern;

a semiconductor device, the semiconductor device adapted to be placed above the interconnect bumps;

a protective layer, the protective layer forming an encapsulant around the semiconductor device;

a ball grid array pattern adapted to be applied to a second side of the substrate;

a solder mask coating applied below the ball grid array pattern; and

a plurality of solder balls attached to the solder mask coating.

8. The packaging of claim 7 wherein the protective layer is selected from a group consisting of a compound, polyimide, resin, or inert metal layer.

9. The packaging of claim 7 wherein the substrate includes a stress relief design.

10. The packaging of claim 9 wherein the stress relief design is a star design.

11. The packaging of claim 9 wherein the stress relief design is a cartesian design.

12. The packaging of claim 7 further comprising a thinning process.

13. The packaging of claim 12 further comprising a carrier removal process.