Substrate Based Fan-Out Wafer Level Packaging
First Claim
1. A method for manufacturing substrate based fan-out wafer level packaging, comprising:
- providing a substrate;
applying a first photoresist pattern;
depositing copper or a copper alloy on said first photoresist pattern;
applying a second photoresist pattern;
forming chip attach site pillars by depositing a layer of copper or copper alloy on said second photoresist pattern;
attaching a semiconductor device via a flip chip bonding, the attaching including;
forming a plurality of interconnect bumps between the semiconductor device and the chip attach site; and
forming a space between the semiconductor device and the substrate;
encapsulating the semiconductor device with a protective layer;
thinning a second side of the substrate, the thinning including copper etching and thinning;
applying a ball grid array pattern on the second side, the ball grid array pattern including a stress relief pattern, the stress relief pattern implemented on the ball grid array pattern and forming a relief of stress for the packaging;
etching the second side with copper;
applying a solder mask coating;
attaching a plurality of ball drops; and
singulating a unit.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.
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Citations
17 Claims
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1. A method for manufacturing substrate based fan-out wafer level packaging, comprising:
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providing a substrate; applying a first photoresist pattern; depositing copper or a copper alloy on said first photoresist pattern; applying a second photoresist pattern; forming chip attach site pillars by depositing a layer of copper or copper alloy on said second photoresist pattern; attaching a semiconductor device via a flip chip bonding, the attaching including; forming a plurality of interconnect bumps between the semiconductor device and the chip attach site; and forming a space between the semiconductor device and the substrate; encapsulating the semiconductor device with a protective layer; thinning a second side of the substrate, the thinning including copper etching and thinning; applying a ball grid array pattern on the second side, the ball grid array pattern including a stress relief pattern, the stress relief pattern implemented on the ball grid array pattern and forming a relief of stress for the packaging; etching the second side with copper; applying a solder mask coating; attaching a plurality of ball drops; and singulating a unit. - View Dependent Claims (2, 3, 4, 14, 15, 16, 17)
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5. (canceled)
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6. (canceled)
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7. A substrate based fan-out wafer level packaging, comprising:
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a substrate; a first photoresist pattern, the first photoresist pattern adapted to be applied to the substrate; a copper or copper alloy layer, the copper or copper alloy layer adapted to be applied on top of the first photoresist pattern; a second photoresist pattern, the second photoresist pattern adapted to be applied above the copper or copper alloy layer; a plurality of chip attach site pillars, the chip attach site pillars including a plurality of interconnect bumps and formed on top of said second photoresist pattern; a semiconductor device, the semiconductor device adapted to be placed above the interconnect bumps; a protective layer, the protective layer forming an encapsulant around the semiconductor device; a ball grid array pattern adapted to be applied to a second side of the substrate; a solder mask coating applied below the ball grid array pattern; and a plurality of solder balls attached to the solder mask coating. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification