WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS

• US 20180130801A1
• Filed: 06/26/2015
• Published: 05/10/2018
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Metz, Matthew V., Dewey, Gilbert, Mohapatra, Chandra S., Kavalieros, Jack T., Murthy, Anand S., Rahhal-Orabi, Nadia M., Ghani, Tahir
• Granted Patent: US 10,461,082 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

Claims

1-20. -20. (canceled)

21. Integrated circuit (IC) structures, comprising:

a well recess in a first region of a substrate, the well recess containing an amorphous well-isolation material over a bottom of the well recess, and a crystalline well material over the well-isolation material, wherein the well material is coupled to a seeding surface of the substrate at the bottom of the well recess by a crystalline pillar material that extends through the well-isolation material;

an amorphous fin-isolation material over the well recess and over a second region of the substrate adjacent to the first region;

a first fin comprising a first crystalline material, wherein the first fin extends from the well material and protrudes through the fin-isolation material; and

a second fin a second crystalline material, wherein the second fin extends from the second region of the substrate and protruding through the fin-isolation material.

22. The IC structures of claim 21, wherein a minimum lateral dimension of the well recess is at least an order of magnitude larger than a longest lateral dimension of the pillar material.

23. The IC structures of claim 21, wherein the fin-isolation material extends around a sidewall of the well material, electrically insulating the well material from the second region of the substrate.

24. The IC structures of claim 23, wherein the fin-isolation material contacts the well-isolation material.

25. The IC structures of claim 21, wherein:

the first fin has a threading dislocation density that is at least three orders of magnitude smaller than that of the pillar material.

26. The IC structure of claim 22, wherein:

a minimum lateral dimension of the well recess is at least 100 μ

m;

a longest lateral dimension of the pillar material is less than 4 μ

m;

the pillar material has an aspect ratio of at least 2;

1; and

a minimum lateral dimension of the first fin is less than 10 nm and the minimum lateral dimension of the second fin is less than 10 nm.

27. The IC structures of claim 21, wherein:

a first surface of the well material from which the first fin extends is planar with a second surface in the second region from which the second fin extends.

28. The IC structures of claim 21, wherein the well recess is a first well recess and the IC structure further comprises:

a second well recess in the second region of the substrate, the second well recess containing a crystalline well material comprising Ge; and

wherein second fin comprises at least one of Si and Ge.

29. The IC structures of claim 21, wherein:

the pillar material comprises a Group III-V alloy and a first heterojunction comprises the pillar material and the substrate; and

a second heterojunction comprises the first crystalline material and the well material.

30. The IC structures of claim 29, wherein:

the substrate comprises silicon;

the first fin comprises at least one of In, Ga, and As; and

the second fin comprises silicon.

31. An integrated circuit (IC), comprising:

an n-type finFET extending from one body of crystalline III-V material, the crystalline III-V material within a well recess in a first region of a crystalline silicon substrate, the well recess lined with a dielectric material, and wherein one or more pillars of the crystalline III-V material extend through the well-isolation material and couple to a seeding surface of the substrate; and

a p-type finFET in a second region of the crystalline silicon substrate.

32. The IC of claim 31, wherein:

the n-type finFET is one of a plurality of n-type finFETs over a first lateral dimension of the well recess; and

the one or more pillars of crystalline III-V material comprises a plurality of pillars arrayed over the first lateral dimension and a second lateral dimension, orthogonal to the first lateral dimension.

33. A method of fabricating a pair of complementary field effect transistors, the method comprising:

etching a well within a first region of a crystalline silicon substrate;

backfilling the well with a dielectric material;

forming one or more openings through the dielectric material that expose the substrate at a bottom of the well;

epitaxially growing a crystalline pillar comprising a Group III-V alloy on the substrate expose within the openings;

laterally overgrowing a III-V material from the pillar;

planarizing the III-V material with a second region of the substrate;

forming first fins in the III-V material, and forming second fins in the second region;

forming first gate stacks over the first fins, and forming second gate stacks of the second fins; and

forming contact metallization to a source and drain ends of the first and second fins.

34. The method of claim 33, further comprising depositing a second dielectric material over the first and second fins, the second dielectric material covering a sidewall of the III-V material.

35. The method of claim 34, further comprising laterally separating the laterally overgrown III-V material from a crystalline material in the second region by depositing the second dielectric material on the first dielectric material.

36. The method of claim 34, further comprising:

forming an amorphous spacer material on a sidewall of the well not covered by the dielectric material; and

removing the spacer material before depositing the second dielectric material into a recess left by the spacer material removal.

37. The method of claim 33, wherein the well is a first well, and the method further comprises:

etching a second well within the second region;

epitaxially growing a well material comprising Ge within the second well; and

etching the second fins into the well material comprising Ge.

38. The method of claim 33, wherein:

forming the openings through the well-isolation material further comprises etching an opening having a longest lateral dimension that is at least an order of magnitude smaller than a minimum lateral dimension of the well.

39. The method of claim 33, wherein:

growing the pillar and laterally overgrowing the III-V material from the pillar further comprises growing a first alloy comprising GaAs, InP, InAs, InGaAs, AlGaAs, GaP, AlAs, or InGaP; and

a remainder of the well is backfilled with a III-V material by heteroepitaxially growing a second alloy comprising GaAs, InP, InAs, InGaAs, AlGaAs, GaP, AlAs, or InGaP.

40. The method of claim 33, further comprising:

masking the planarized III-V material;

etching a second well in a second region of the substrate;

heteroepitaxially growing a material comprising Ge in the second well; and

planarizing a surface of the material comprising Ge with a surface of the III-V material.