THREE-DIMENSIONAL MEMORY DEVICE WITH ELECTRICALLY ISOLATED SUPPORT PILLAR STRUCTURES AND METHOD OF MAKING THEREOF
First Claim
1. A three-dimensional memory device comprising:
- a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate;
a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings;
a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically shorted to a horizontal semiconductor channel located within the substrate;
a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate; and
a first epitaxial pedestal located at a bottom portion of the memory opening and contacting the vertical semiconductor channel and the substrate; and
a second epitaxial pedestal located at a bottom portion of the support opening and comprising a same material as the first epitaxial pedestal and vertically spaced from a bottommost surface of the vertical semiconductor layer,wherein;
the first epitaxial pedestal has a greater height than the second epitaxial pedestal; and
the three-dimensional memory device comprises a feature selected from;
a first feature that the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and a subset of the first electrically conductive layers; and
a second feature that the first epitaxial pedestal has a substantially same height as the second epitaxial pedestal, and the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.
40 Citations
39 Claims
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1. A three-dimensional memory device comprising:
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a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate; a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure; a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate; a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings; a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically shorted to a horizontal semiconductor channel located within the substrate; a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate; and a first epitaxial pedestal located at a bottom portion of the memory opening and contacting the vertical semiconductor channel and the substrate; and a second epitaxial pedestal located at a bottom portion of the support opening and comprising a same material as the first epitaxial pedestal and vertically spaced from a bottommost surface of the vertical semiconductor layer, wherein; the first epitaxial pedestal has a greater height than the second epitaxial pedestal; and the three-dimensional memory device comprises a feature selected from; a first feature that the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and a subset of the first electrically conductive layers; and a second feature that the first epitaxial pedestal has a substantially same height as the second epitaxial pedestal, and the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer. - View Dependent Claims (2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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3. (canceled)
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15-26. -26. (canceled)
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27. A three-dimensional memory device comprising:
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a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate; a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure; a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate; a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings; a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically shorted to a horizontal semiconductor channel located within the substrate; a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate; a first semiconductor oxide portion having an annular shape and laterally surrounding a bottom portion of the vertical semiconductor channel, wherein the dielectric material portion comprises a second semiconductor oxide portion underlying the vertical semiconductor layer having a same composition as the first semiconductor oxide portion; a metal oxide etch stop portion located above the second semiconductor oxide portion, wherein; the second semiconductor oxide portion underlies the metal oxide etch stop portion; and the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A three-dimensional memory device comprising:
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a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate; a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure; a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate; a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings; a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically shorted to a horizontal semiconductor channel located within the substrate; and a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate, wherein; the memory stack structure comprises a memory film including a first layer stack; the support pillar structure comprises a second layer stack, wherein each layer within the second layer stack has a same thickness and a same material composition as a corresponding layer within the first layer stack; and a bottommost surface of the second layer stack contacts a top surface of the dielectric material portion, wherein the top surface of the dielectric material portion is located between a topmost layer among the first electrically conductive layers and a bottommost layer among the first electrically conductive layers. - View Dependent Claims (35, 36, 37, 38, 39)
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39. The three-dimensional memory device of claim 38, wherein:
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the second semiconductor oxide portion has a greater height than the first semiconductor oxide portion; and the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and a subset of the first electrically conductive layers.
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Specification