THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE HAVING THE SAME

• US 20180130827A1
• Filed: 06/28/2017
• Published: 05/10/2018
• Est. Priority Date: 11/04/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, JUN HEE, BAE, IN JUN
• Granted Patent: US 10,236,308 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

A thin film transistor includes a first blocking layer disposed on a substrate, and an active pattern disposed on the first blocking layer. The active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The thin film transistor further includes a gate electrode disposed on the active pattern. The channel region corresponds to a portion of the active pattern overlapped by the gate electrode. The thin film transistor additionally includes a source electrode connected to the source region, and a drain electrode connected to the drain region. The active pattern includes a first part and a second part. The first part partially overlaps with the first blocking layer, and the first part and the second part have different thicknesses from each other.

Claims

1. A thin film transistor comprising:

a first blocking layer disposed on a substrate;

an active pattern disposed on the first blocking layer, wherein the active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region;

a gate electrode disposed on the active pattern, wherein the channel region corresponds to a portion of the active pattern overlapped by the gate electrode; and

a source electrode connected to the source region, and a drain electrode connected to the drain region,

wherein the active pattern includes a first part and a second part, wherein the first part partially overlaps with the first blocking layer, and the first part and the second part have different thicknesses from each other.

2. The thin film transistor of claim 1, wherein the second part of the active pattern does not overlap with the first blocking layer.

3. The thin film transistor of claim 2, wherein a thickness of the first part of the active pattern is less than a thickness of the second part of the active pattern.

4. The thin film transistor of claim 1, wherein the drain region partially overlaps with the first blocking layer.

5. The thin film transistor of claim 4, wherein the active pattern further comprises a drain-channel contact part disposed between the drain region and the channel region,

wherein the drain-channel contact part overlaps with the first blocking layer.

6. The thin film transistor of claim 5, wherein the drain-channel contact part is covered by the first blocking layer to block light that is incident onto a surface of the substrate, on which the active pattern is not disposed.

7. The thin film transistor of claim 6, wherein the drain-channel contact part partially extends into the channel region from a point at which the channel region and the drain region are in contact with each other.

8. The thin film transistor of claim 7, wherein the drain-channel contact part has a width of about 3.5 μ

m or more.

9. The thin film transistor of claim 1, further comprising a second blocking layer partially overlapping with the drain region and the channel region, and

wherein the first blocking layer partially overlaps with the source region and the channel region.

10. The thin film transistor of claim 9, wherein the first blocking layer and the second blocking layer are disposed in the same layer.

11. The thin film transistor of claim 9, wherein the active pattern further comprises a source-channel contact part disposed between the source region and the channel region, and a drain-channel contact part disposed between the drain region and the channel region,

wherein the source-channel contact part overlaps with the first blocking layer, and the drain-channel contact part overlaps with the second blocking layer.

12. The thin film transistor of claim 11, wherein the source-channel contact part is covered by the first blocking layer to block light that is incident onto a surface of the substrate, on which the active pattern is not disposed, and

wherein the drain-channel contact part is covered by the second blocking layer to block light that is incident onto the first surface of the substrate.

13. The thin film transistor of claim 12, wherein the source-channel contact part partially extends into the channel region from a point at which the channel region and the source region are in contact with each other, and

wherein the drain-channel contact part partially extends into the channel region from a point at which the channel region and the drain region are in contact with each other.

14. The thin film transistor of claim 13, wherein each of the source-channel contact part and the drain-channel contact part has a width of about 3.5 μ

m or more.

15. The thin film transistor of claim 1, wherein the first blocking layer overlaps with the channel region, the source region, and the drain region.

16. The thin film transistor of claim 1, wherein the first blocking layer includes a metal.

17. A method of manufacturing a thin film transistor, the method comprising:

forming a blocking layer on a substrate;

forming a buffer layer over the blocking layer;

forming a semiconductor layer on the buffer layer, the semiconductor layer including a first part and a second part, wherein the first part and the second part have different thicknesses from each other;

forming a gate insulating layer over the semiconductor layer;

forming a gate electrode covering a region of the semiconductor layer on the gate insulating layer;

forming an active pattern by doping impurities on the substrate on which the gate electrode is formed, wherein the active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region;

forming a source electrode connected to the source region; and

forming a drain electrode connected to the drain region.

18. The method of claim 17, wherein the forming of the semiconductor layer includes:

coating the buffer layer with a semiconductor material layer; and

performing a planarization process on the semiconductor material layer.

19. The method of claim 17, wherein the first part of the semiconductor layer overlaps with the blocking layer, and the second part of the semiconductor layer does not overlap with the blocking layer.

20. The method of claim 19, wherein a thickness of the first part of the semiconductor layer is less than a thickness of the second part of the semiconductor layer.

21. A display device comprising:

a display element; and

a thin film transistor connected to the display element,

wherein the thin film transistor includes;

a first blocking layer disposed on a substrate;

an active pattern disposed on the first blocking layer, wherein the active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region;

a gate electrode disposed on the active pattern, wherein the channel region corresponds to a portion of the active pattern overlapping by the gate electrode; and

a source electrode connected to the source region, and a drain electrode connected to the drain region,

wherein the active pattern includes a first part and a second part, wherein the first part partially overlaps with the first blocking layer, and the first part and the second part have different thicknesses from each other.

22. The display device of claim 21, wherein the second part of the active pattern does not overlap with the first blocking layer.

23. The display device of claim 22, wherein a thickness of the first part of the active pattern is less than a thickness of the second part of the active pattern.

24. The display device of claim 21, wherein the drain region partially overlaps with the first blocking layer.

25. The display device of claim 24, wherein the active pattern further comprises a drain-channel contact part disposed between the drain region and the channel region,

wherein the drain-channel contact part overlaps with the first blocking layer.

26. The display device of claim 25, wherein the drain-channel contact part is covered by the first blocking layer to block light that is incident onto a surface of the substrate, on which the active pattern is not disposed.

27. The display device of claim 26, wherein the drain-channel contact part partially extends into the channel region from a point at which the channel region and the drain region are in contact with each other.

28. The display device of claim 27, wherein the drain-channel contact part has a width of about 3.5 μ

m or more.

29. The display device of claim 21, further comprising a second blocking layer partially overlapping with the drain region and the channel region, and

wherein the first blocking layer partially overlaps with the source region and the channel region.

30. The display device of claim 29, wherein the first blocking layer and the second blocking layer are disposed in the same layer.

31. The display device of claim 29, wherein the active pattern further comprises a source-channel contact part disposed between the source region and the channel region, and a drain-channel contact part disposed between the drain region and the channel region,

wherein the source-channel contact part overlaps with the first blocking layer, and the drain-channel contact part overlaps with the second blocking layer.

32. The display device of claim 31, wherein the source-channel contact part is covered by the first blocking layer to block light that is incident onto a surface of the substrate, on which the active pattern is not disposed, and

wherein the drain-channel contact part is covered by the second blocking layer to block light that is incident onto the surface of the substrate, on which the active pattern is not disposed.

33. The display device of claim 32, wherein the source-channel contact part partially extends into the channel region from a point at which the channel region and the source region are in contact with each other, and

wherein the drain-channel contact part partially extends into the channel region from a point at which the channel region and the drain region are in contact with each other.

34. The display device of claim 33, wherein each of the source-channel contact part and the drain-channel contact part has a width of about 3.5 μ

m or more.

35. The display device of claim 21, wherein the first blocking layer overlaps with the channel region, the source region, and the drain region.

36. The display device of claim 21, wherein the display element includes:

a first electrode connected to the drain electrode of the thin film transistor;

an emitting layer disposed on the first electrode; and

a second electrode disposed on the emitting layer.