SYSTEMS AND METHOD FOR MAPPING FIFOS TO PROCESSOR ADDRESS SPACE
First Claim
1. A microprocessor computer system comprising:
- a processor core capable of at least one ofreading data from a separate storage means by presenting an address and retrieving data; and
writing data to a separate storage means by presenting an address and data to be stored by said storage means;
a storage means comprising at least one bank of at least one hardware first in first out (FIFO), said FIFO further comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in the FIFO;
wherein at least one of said FIFO head and FIFO tail is addressable by said processor core and mapped to at least one fixed memory address; and
busses and control signals to operably couple said processor core and said hardware FIFO, wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty.
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Accused Products
Abstract
An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.
17 Citations
35 Claims
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1. A microprocessor computer system comprising:
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a processor core capable of at least one of reading data from a separate storage means by presenting an address and retrieving data; and writing data to a separate storage means by presenting an address and data to be stored by said storage means; a storage means comprising at least one bank of at least one hardware first in first out (FIFO), said FIFO further comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in the FIFO; wherein at least one of said FIFO head and FIFO tail is addressable by said processor core and mapped to at least one fixed memory address; and busses and control signals to operably couple said processor core and said hardware FIFO, wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 35)
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26. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises
a processor core capable of at least one of reading data from a storage means by presenting a memory address and retrieving data and writing data to a storage means by presenting a memory address and data to be stored by said storage means; -
a storage means comprising at least one bank of at least one hardware first in first out hardware FIFO, said hardware FIFO comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in said hardware FIFO, wherein at least one of said hardware FIFO head and hardware FIFO tail is addressable by said processor core and mapped to at least one fixed said memory address; busses and control signals to operably couple said processor core and said hardware FIFO wherein said busses transfer addresses and data between said processor core and said hardware FIFO; and control signals for indicating failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty; a FIFO controller comprising at least one of a state machine and a programmable microcontroller that is configured to control operations on said hardware FIFO and a set of configuration and status registers; and a new data packet configuration comprising a header of any length and data of any length; wherein said method comprises the steps of; filling with new data packet at said tail and advancing towards said head of said hardware FIFO as prior data packets are dequeued; detecting said new data packet header at said head of said hardware FIFO; determining if said FIFO controller has already been configured to process said new data packet; when said FIFO controller has not been configured to process said new data packet header, sending from said FIFO controller to said processor core an interrupt; and wherein said processor core; dequeues and processes said new data packet'"'"'s header; performs any operations that precede packet data processing; and configures said FIFO controller for processing a remainder of said new data packet; processing by said configured FIFO controller of said new data packet according to said configuration until, and in accordance with a FIFO controller configuration, a termination condition is satisfied; when said FIFO controller is configured to interrupt said processor core at a completion of said processing; interrupting said processor core; and whereupon said processor core inspects said FIFO configuration and status registers and completes processing of said new data packet. - View Dependent Claims (27)
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28. A method of configuring a microprocessor computer system that comprises
a processor core capable of at least one of reading data from a storage means by presenting an address; - and
retrieving data and writing data to a storage means by presenting an address and data to be stored by said storage means; said storage means comprising at least one bank of at least one hardware first in first out (FIFO) queue, denoted hardware FIFO, comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in the FIFO wherein at least one of said FIFO head and FIFO tail is addressable by said processor core and mapped to at least one fixed memory address; busses and control signals to operably couple said processor core and said hardware FIFO wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty; a FIFO controller comprising at least one of a state machine and a programmable microcontroller that is configured to control operations on said hardware FIFO and a set of configuration and status registers; wherein said method comprising the steps of; configuring by said processor core, said FIFO controller to retrieve and process data from at least one of cache memory, other memory, as at least one of memory-mapped FIFO; writing by said processor core, any required header data to said FIFO prior initiating FIFO controller processing; initiating by said processor core, FIFO controller processing using said configuration, the following steps until FIFO controller satisfies termination condition specified in said configuration; computing an address of a next data item according to said configuration; retrieving said next data item from said address and processing said next data item according to said configuration; and when said FIFO controller is configured to interrupt said processor core at the completion of said processing, interrupting said processor core, whereupon said processor core inspects said FIFO configuration and status registers and completes processing. - View Dependent Claims (29, 30)
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31. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises
a processor core capable of at least one of reading data from a storage means by presenting an address and retrieving data; - and
writing data to a storage means by presenting an address and data to be stored by said storage means; a storage means comprising at least one bank of at least one hardware first in first out (FIFO) queue comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in said hardware FIFO wherein at least one of said hardware FIFO head and said hardware FIFO tail is addressable by said processor core and mapped to at least one fixed memory address; busses and control signals to operably couple said processor core and said hardware FIFO wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty; and when a bit width of said hardware FIFO tail exceeds a bit width of said processor core'"'"'s ability to write to said hardware FIFO tail in a single write operation, said method comprises the steps of performing a sequence of non-enqueuing write operations until an occurrence of a last word to be written; and performing an enqueuing write for the last write operation that commits said word to said hardware FIFO.
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32. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises:
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a processor core capable of at least one of reading data from a storage means by presenting an address; and retrieving data and writing data to a storage means by presenting an address and data to be stored by said storage means, said storage means comprising at least one bank of at least one hardware first in first out (FIFO) queue, denoted hardware FIFO, comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in the FIFO wherein at least one of said FIFO head and FIFO tail is addressable by the processor core and mapped to at least one fixed memory address, busses and control signals to operably couple said processor core and said hardware FIFO wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty, wherein when bit width of said FIFO head exceeds bit width of said processor core'"'"'s ability to read from said FIFO head in a single read operation, said method comprises performing a sequence of non-dequeuing read operations until an occurrence of a last word to be read; and performing a dequeuing read for said last read operation that removes said word from said hardware FIFO.
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33. A method for configuring a microprocessor computer system, wherein said microprocessor computer system comprises a processor core executing vector operations and at least one memory-mapped FIFO;
said method comprising the steps of; filling said at least one memory-mapped FIFO with vector data as needed; and performing said vector operation repeatedly to process each element of said vector data by; dequeuing a value from said at least one memory-mapped FIFO; and processing said value according to an operation to be performed.
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34. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises a processor core executing vector operations and at least one memory-mapped FIFO;
said method comprising the steps of; performing said vector operation repeatedly to generate each value of an vector result comprising the steps; executing an iteration of said vector operation resulting in an element of an output vector, enqueuing said value onto said at least one memory-mapped FIFO.
Specification