METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE
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Accused Products
Abstract
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
199 Citations
20 Claims
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1. (canceled)
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2. A method for manufacturing a semiconductor device, the method comprising steps of:
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forming a gate electrode layer over an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer comprising a channel formation region over the gate insulating layer; forming a silicon oxide insulating layer over the oxide semiconductor layer; forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers a periphery of the oxide semiconductor layer; forming a source electrode layer electrically connected to the oxide semiconductor layer through the first opening; and forming a drain electrode layer electrically connected to the oxide semiconductor layer through the second opening, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the gate electrode layer is formed using a gate wiring layer, wherein the source electrode layer is formed using a source wiring layer, and wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate insulating layer and the silicon oxide insulating layer are interposed between the gate wiring layer and the source wiring layer. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A method for manufacturing a semiconductor device, the method comprising steps of:
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forming a gate electrode layer over an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer comprising a channel formation region over the gate insulating layer; forming a silicon oxide insulating layer over the oxide semiconductor layer; forming a first opening and a second opening in the silicon oxide insulating layer so that the silicon oxide insulating layer covers a periphery of the oxide semiconductor layer; forming a source electrode layer electrically connected to the oxide semiconductor layer through the first opening; forming a drain electrode layer electrically connected to the oxide semiconductor layer through the second opening; forming an inorganic insulating film over the source electrode layer and the drain electrode layer; forming a third opening in the inorganic insulating film; and forming a pixel electrode layer electrically connected to one of the source electrode layer and the drain electrode layer through the third opening, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the gate electrode layer is formed using a gate wiring layer, wherein the source electrode layer is formed using a source wiring layer, and wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate insulating layer and the silicon oxide insulating layer are interposed between the gate wiring layer and the source wiring layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for manufacturing a semiconductor device, the method comprising steps of:
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forming a gate electrode layer over an insulating surface; forming a gate insulating layer over the gate electrode layer; forming a semiconductor layer comprising a channel formation region over the gate insulating layer; forming a first insulating layer over the semiconductor layer; forming a first opening and a second opening in the first insulating layer so that the first insulating layer covers a periphery of the semiconductor layer; forming a source electrode layer electrically connected to the semiconductor layer through the first opening; and forming a drain electrode layer electrically connected to the semiconductor layer through the second opening, wherein the gate electrode layer is formed using a gate wiring layer, wherein the source electrode layer is formed using a source wiring layer, and wherein, in a wiring intersection of the gate wiring layer and the source wiring layer, the gate insulating layer and the first insulating layer are interposed between the gate wiring layer and the source wiring layer. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification