Deep Trench MOS Barrier Junction All Around Rectifier and MOSFET

• US 20180138322A1
• Filed: 12/23/2017
• Published: 05/17/2018
• Est. Priority Date: 09/03/2016
• Status: Active Grant

• Current Assignee: Champion Microelectronic Corporation, Ho-Yuan Yu
• Original Assignee: Champion Microelectronic Corporation, Yutechnix, Inc.
• Inventors: Dun, Haiping, Yu, Ho-Yuan, Lin, Hung-Chen
• Granted Patent: US 10,770,599 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N− epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N− epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions. In a further embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create yet another device with very high breakdown voltage and very low leakage current. This structure can be extended to multiple deep trenches and shallow trenches as well.

Claims

1. A rectifier device, comprising:

a first n-type semiconductor layer;

a second n-type epitaxial semiconductor layer with lower doping concentration but larger depth than that of the first n-type semiconductor layer, deposed on top of the first n-type semiconductor layer;

a third p-type semiconductor layer deposed on top of the second n-type semiconductor layer;

a first enclosed deep trench etched in ring shape along periphery of the rectifier device and from top of the third p-type semiconductor layer down to bottom the second n-type semiconductor layer; and

a second enclosed deep trench running parallel to the first enclosed deep trench but with smaller radius, etched from the top of the third p-type semiconductor layer down to the bottom the second n-type semiconductor layer;

wherein both the first and second enclosed deep trenches have substantially the same depth.

2. The rectifier device of claim 1, wherein the third p-type semiconductor layer are two regions in ring shape that cover only part of the second n-type semiconductor layer, and the first region of the third p-type semiconductor layer runs parallel to and has wider width than the first enclosed deep trench, and the second region of the third p-type semiconductor layer runs parallel to and has wider width than the second enclosed deep trench.

3. The rectifier device of claim 1, further comprising two fourth n-type semiconductor regions deposed in upper part of the third p-type semiconductor layer and on both sides of the first enclosed deep trench, and two more fourth n-type semiconductor regions deposed in upper part of the third p-type semiconductor layer and on both sides of the second enclosed deep trench, such that all the fourth n-type semiconductor regions are in ring shape, wherein the fourth n-type regions have higher doping concentration than the second n-type semiconductor layer.

4. The rectifier device of claim 1, further comprising a fourth n-type semiconductor layer deposed above the third p-type semiconductor layer, and both the first enclosed deep trench and the second enclosed deep trench are etched from the top of the fourth n-type semiconductor layer down to the bottom the second n-type semiconductor layer, wherein fourth n-type semiconductor has higher doping concentration than the second n-type semiconductor layer.

5. The rectifier device of claim 4, further comprising an enclosed shallow trench in ring shape between the first and second enclosed deep trench, etched from the top of the fourth n-type semiconductor layer down to slightly below the interface between the second n-type semiconductor layer and the third p-semiconductor layer, wherein the enclosed shallow trench has oxide layer on its sidewalls and bottom surface, and a polysilicon layer above the oxide layer.

6. The rectifier device of claim 1, wherein the first enclosed deep trench and the second enclosed deep trench are etched down to the first n-type semiconductor layer, close to the bottom of the rectifier device.

7. The rectifier device of claim 1, wherein both the first enclosed deep trench and the second enclosed deep trench have an oxide layer on their sidewalls and bottom surface, and a polysilicon layer above the oxide layer.

8. A MOSFET, comprising:

a first semiconductor layer of a first type of dopant;

a second semiconductor layer of the first type of dopant deposed above the first semiconductor layer, and with lower doping concentration but larger depth than that of the first semiconductor layer;

a third semiconductor layer of a second type of dopant deposed above the second semiconductor layer, wherein the first type of dopant and the second type of dopant have opposite polarity;

a fourth semiconductor layer of the first type of dopant deposed above the third semiconductor layer, and with higher doping concentration than that of the second semiconductor layer; and

a first enclosed deep trench etched from top of the fourth semiconductor layer down to bottom of the second semiconductor layer, and along the periphery of the MOSFET, with oxide layer on its sidewalls and bottom surface, and a polysilicon layer above the oxide layer.

9. The MOSFET of claim 8, further comprising a second enclosed deep trench etched from the top of the fourth semiconductor layer down to the second semiconductor layer, and running parallel to and with smaller radius than the first enclosed deep trench, wherein both the first and second enclosed deep trenches have substantially the same depth.

10. The MOSFET of claim 8, wherein the first type of dopant is N-type and the second type of dopant is P-type.

11. The MOSFET of claim 8, further comprising an enclosed shallow trench in center of the MOSFET, etched from top of the fourth semiconductor layer down to the second semiconductor layer, but close to the interface between the second and third semiconductor layer, wherein the enclosed shallow trench has an oxide layer on their sidewalls and bottom surface, and a polysilicon layer above the oxide layer to act as gate of the MOSFET.

12. The MOSFET of claim 9, further comprising an enclosed shallow trench etched from top surface of the fourth semiconductor layer down to the second semiconductor layer but close to the interface between the second and third semiconductor layers, wherein the enclosed shallow trench runs parallel to and is between the first and second enclosed deep trenches and acts as gate of the MOSFET.

13. The MOSFET of claim 9, wherein both the first and second enclosed deep trenches are etched down to the first semiconductor layer, close to the bottom of the MOSFET.

14. The MOSFET of claim 12, wherein the first enclosed deep trench, second enclosed deep trench, and the enclosed shallow trench are in ring shape, and the depth of the enclosed shallow trench is about a quarter of both first and second enclosed deep trenches.

15. A MOSFET, comprising:

a first semiconductor layer of a first type of dopant;

a second semiconductor layer of the first type of dopant deposed above the first semiconductor layer, and with lower doping concentration but larger depth than that of the first semiconductor layer;

a third semiconductor layer of a second type of dopant deposed above the second semiconductor layer, wherein the first type of dopant and the second type of dopant have opposite polarity; and

a first enclosed deep trench etched from top of the third semiconductor layer down to bottom of the second semiconductor layer, and along the periphery of the MOSFET; and

two fourth semiconductor regions of the first type of dopant deposed in the upper part of the third semiconductor layer and on both sides of the first enclosed deep trench, wherein the first enclosed deep trench has oxide layer on its sidewalls and bottom surface, and a polysilicon layer above the oxide layer.

16. The MOSFET of claim 15, further comprising a second enclosed deep trench etched from top of the third semiconductor layer down to bottom of the second semiconductor layer, and running parallel to and with smaller radius than the first enclosed deep trench, wherein both the first and second enclosed deep trenches have substantially the same depth, wherein two fourth semiconductor regions of the first type of dopant deposed in the upper part of the third semiconductor layer and on both sides of the second enclosed deep trench.

17. The MOSFET of claim 15, wherein the first type of dopant is N-type and the second type of dopant is P-type.

18. The MOSFET of claim 16, wherein both the first and second enclosed deep trenches are etched down to the first semiconductor layer, close to the bottom of the MOSFET.