MULTIVALENT OXIDE CAP FOR ANALOG SWITCHING RESISTIVE MEMORY

• US 20180138401A1
• Filed: 12/22/2017
• Published: 05/17/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ando, Takashi, Khater, Marwan H., Kim, Seyoung, Miyazoe, Hiroyuki
• Granted Patent: US 10,797,235 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A memory includes a base oxide provided between a first electrode and a second electrode, and a multivalent oxide provided between the first electrode and the second electrode. The multivalent oxide switches between at least two oxidative states.

Claims

1. A memory, comprising:

a base oxide provided between a first electrode and a second electrode; and

a multivalent oxide provided between the first electrode and the second electrode,

wherein the multivalent oxide switches between at least two oxidative states.

2. The memory according to claim 1, wherein the oxidative states of multivalent oxide is varying during a resistance switching cycle.

3. The memory according to claim 1, wherein the multivalent oxide comprises at least one of CeO_x, PrO_x, EuO_x, and VO_x.

4. The memory according to claim 1, wherein the base oxide comprises at least one of HfO_x and TaO_x.

5. The memory according to claim 1,

wherein the base oxide is provided on the first electrode, and

wherein the multivalent oxide is provided on the base oxide.

6. The memory according to claim 1,

wherein the multivalent oxide is provided on the first electrode, and

wherein the base oxide is provided on the multivalent oxide.

7. The memory according to claim 1,

wherein the multivalent oxide is provided between the base oxide,

wherein the base oxide is provided on the first electrode, and

wherein the second electrode is provided on the base oxide.

8. The memory according to claim 1,

wherein the base oxide is doped with the multivalent oxide to form a doped oxide layer,

wherein the doped oxide layer is provided on the first electrode, and

wherein the second electrode is provided on the doped oxide layer.

9. A semiconductor apparatus, comprising:

a base oxide formed on a first electrode; and

a multivalent oxide formed on the first electrode,

wherein the multivalent oxide switches between at least two oxidative states.

10. The semiconductor apparatus according to claim 9, further comprising:

a second electrode formed on the base oxide and the multivalent oxide and above the first electrode.

11. The semiconductor apparatus according to claim 9, wherein the oxidative states of multivalent oxide is varying during a resistance switching cycle.

12. The semiconductor apparatus according to claim 9, wherein the multivalent oxide comprises at least one of CeO_x, PrO_x, EuO_x, and VO_x.

13. The semiconductor apparatus according to claim 9, wherein the base oxide comprises at least one of HfO_x and TaO_x.

14. The semiconductor apparatus according to claim 9,

wherein the base oxide is provided on the first electrode, and

wherein the multivalent oxide is provided on the base oxide.

15. The semiconductor apparatus according to claim 9,

wherein the multivalent oxide is provided on the first electrode, and

wherein the base oxide is provided on the multivalent oxide.

16. The semiconductor apparatus according to claim 9,

wherein the multivalent oxide is provided between the base oxide,

wherein the base oxide is provided on the first electrode, and

wherein the second electrode is provided on the base oxide.

17. The semiconductor apparatus according to claim 9,

wherein the base oxide is doped with the multivalent oxide to form a doped oxide layer,

wherein the doped oxide layer is provided on the first electrode, and

wherein the second electrode is provided on the doped oxide layer.

18. A method of forming a memory, the method comprising:

forming a base oxide between a first electrode and a second electrode; and

forming a multivalent oxide between the first electrode and the second electrode,

wherein the multivalent oxide switches between at least two oxidative states.

19. The method according to claim 18, wherein the oxidative states of multivalent oxide is varying during a resistance switching cycle.

20. The method according to claim 18,

wherein the multivalent oxide comprises at least one of CeO_x, PrO_x, EuO_x, and VO_x, and

wherein the base oxide comprises at least one of HfO_x and TaO_x.