FRACTIONAL-N JITTER ATTENUATOR

• US 20180138915A1
• Filed: 06/02/2017
• Published: 05/17/2018
• Est. Priority Date: 11/16/2016
• Status: Active Grant

• Current Assignee: Perceptia IP Pty., Ltd.
• Original Assignee: Perceptia Devices, Inc.
• Inventors: Jenkins, Julian, Grouwstra, Andr
• Granted Patent: US 9,991,898 B1
• Time in Patent Office: Days
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

Claims

1. A fractional-N jitter attenuator, comprising:

(a) a primary loop, including;

(i) a primary counter with an input and an output, wherein the primary counter may include a modulo-K counter;

(ii) a primary register with a first input coupled with the primary counter output and a second input configured for receiving a primary reference clock signal, wherein the primary register is configured to store a primary sampled phase from the primary counter output upon receiving a primary reference clock signal pulse;

(iii) a primary fractional phase predictor with a first input configured for receiving the primary reference clock signal, wherein the primary fractional phase predictor is configured to calculate a primary predicted phase upon receiving a primary reference clock signal pulse, and wherein the primary predicted phase includes an integer number and is based on a rational number primary frequency control word (FCW);

(iv) one of a primary subtractor and a primary adder, configured for calculating an integer number primary difference between the primary predicted phase and the primary sampled phase;

(v) a primary loop filter, configured to receive the primary integer number difference, and to provide a primary loop filtering action to generate a secondary FCW; and

(b) a secondary loop including a fractional-N PLL with a first input configured for receiving a stable reference clock signal, a second input configured for receiving the secondary FCW, and an output configured to provide an output clock signal based on the stable reference clock signal and the secondary FCW, the secondary loop output being coupled with the primary counter input and with a fractional-N jitter attenuator output.

2. The fractional-N jitter attenuator of claim 1, wherein the secondary loop comprises:

a controlled oscillator with an output coupled with the secondary loop output, wherein the controlled oscillator is configured to produce an output clock signal at its output;

a secondary counter with an input and an output, wherein the input is coupled with the controlled oscillator output, and wherein the secondary counter may include a modulo-K counter;

a secondary register with a first input coupled with the secondary counter output and a second input configured for receiving the stable reference clock signal, wherein the secondary register is configured to store a secondary sampled phase from the secondary counter output upon receiving a stable reference clock signal pulse;

a secondary phase predictor with a first input configured for receiving the stable reference clock signal, wherein the secondary phase predictor is configured to calculate a secondary predicted phase based on the secondary FCW upon receiving a stable reference clock signal pulse;

one of a secondary subtractor and a secondary adder, configured for calculating a secondary difference between the secondary predicted phase and the secondary sampled phase; and

a secondary loop filter configured to receive the secondary difference and provide a secondary loop filtering action to generate an oscillator control code, the oscillator control code being forwarded to the controlled oscillator and controlling a controlled oscillator frequency.

3. The fractional-N jitter attenuator of claim 2, wherein the primary and the secondary counters are combined into a single counter.

4. The fractional-N jitter attenuator of claim 1, wherein a primary loop filter bandwidth is at least one hundred times smaller than a secondary loop filter bandwidth.

5. The fractional-N jitter attenuator of claim 1, further comprising a time-to-digital converter coupled with the controlled oscillator output, and configured to measure a fraction of a cycle of the output clock signal upon receiving a primary reference clock signal pulse, and wherein the primary sampled phase includes a measured fraction of the cycle.

6. The fractional-N jitter attenuator of claim 2, further comprising a time-to-digital converter coupled with the controlled oscillator output, and configured to measure a fraction of a cycle of the output clock signal upon receiving a stable reference clock pulse, and wherein the secondary sampled phase includes a measured fraction of the cycle.

7. The fractional-N jitter attenuator of claim 1, further comprising a primary sleep signal input coupled with a first input of a gate, and wherein a second input of the gate is configured to receive the primary reference clock signal, the gate providing a gated primary reference clock signal at an output, wherein the gate output is coupled with the primary fractional phase predictor and the primary register.

8. The fractional-N jitter attenuator of claim 1, wherein a range K of the primary counter is at least two times larger than a maximum number of output clock signal cycles during a primary reference clock signal cycle.

9. The fractional-N jitter attenuator of claim 1, wherein the primary fractional phase predictor has a range that is at least two times larger than a maximum number of output clock signal cycles during a primary reference clock signal cycle.

10. The fractional-N jitter attenuator of claim 1, wherein the primary fractional phase predictor includes an interpolator for determining an integer number part of the primary predicted phase based on a fractional part of the FCW.

11. The fractional-N jitter attenuator of claim 10, wherein the interpolator performs a noise-shaping function to move at least a part of quantization noise energy from low frequencies to higher frequencies.

12. The fractional-N jitter attenuator of claim 11, wherein the interpolator includes one of a sigma delta modulator, a bandpass sigma delta modulator, parallel sigma delta modulators, a multistage noise shaping (MASH) modulator, and a sturdy MASH (SMASH) modulator.

13. The fractional-N jitter attenuator of claim 2, further comprising an oscillator sleep signal input, wherein the controlled oscillator is configured to stop operation when it receives an asserted oscillator sleep control signal.

14. The fractional-N jitter attenuator of claim 1, comprising multiple primary loops.

15. The fractional-N jitter attenuator of claim 14, wherein at least one of the multiple primary loops has a monitor-and-adjust function to provide for hitless switching, and wherein the monitor-and-adjust function monitors a primary difference in the one of the multiple primary loops and adjusts a fractional phase predictor value to minimize the primary difference.

16. A method for jitter attenuation, comprising the following steps:

(a) in a primary PLL loop, based on a primary reference clock signal and a rational first frequency control word (FCW), calculating an integer primary predicted phase;

based on the primary reference clock signal and a secondary PLL loop output clock signal, sampling a phase at a counter output to obtain an integer primary sampled phase, wherein the counter may include a modulo-K counter;

calculating a primary difference by subtracting the primary sampled phase from the primary predicted phase;

(b) loop filtering the primary difference in a primary loop filter to obtain a rational second FCW;

(c) forwarding the second FCW to a secondary loop;

(d) based on the second FCW and a secondary reference clock signal, calculating a secondary predicted phase;

based on the secondary reference clock signal and the secondary PLL loop output clock signal, sampling a phase to obtain a secondary sampled phase;

calculating a secondary difference by subtracting the secondary sampled phase from the secondary predicted phase; and

(e) loop filtering the secondary difference in a secondary loop filter to obtain an oscillator control code to control a controlled oscillator and to determine a frequency of the secondary PLL loop output clock signal.

17. A programmable jitter attenuator, comprising:

a fractional-N PLL with a stable reference signal input and a frequency control word (FCW) input, configured to produce an output clock signal at a PLL output;

a counter with an input coupled with the PLL output, wherein the counter may include a modulo-K counter;

a programmable processor with a first input coupled with a counter output, a second input configured for receiving a primary reference clock signal, and an output coupled with the fractional-N PLL FCW input to provide a secondary FCW;

a memory coupled with the programmable processor and configured to store at least one of program instructions or data;

wherein the programmable processor is programmed to execute instructions for the following operations;

(a) in the programmable processor, based on the primary reference clock signal and a rational primary FCW, calculating an integer primary predicted phase;

based on the primary reference clock signal and the fractional-N PLL output clock signal, sampling a phase at the counter output to obtain an integer primary sampled phase;

calculating a primary difference by subtracting the primary sampled phase from the primary predicted phase;

(b) loop filtering the primary difference in a primary loop filter to obtain the secondary FCW; and

(c) forwarding the secondary FCW to the fractional-N PLL to control the fractional-N PLL and to determine a frequency of the fractional-N PLL output clock signal.

18. A tangible non-transitory memory, carrying software instructions for the following operations:

(a) in a programmable processor, based on a primary reference clock signal and a rational primary FCW, calculating an integer primary predicted phase;

based on the primary reference clock signal and a fractional-N PLL output clock signal, sampling a phase at a counter output to obtain an integer primary sampled phase, wherein the counter may include a modulo-K counter;

calculating a primary difference by subtracting the primary sampled phase from the primary predicted phase;

(b) loop filtering the primary difference in a primary loop filter to obtain a rational secondary FCW; and

(c) forwarding the secondary FCW to the fractional-N PLL to control the fractional-N PLL and to determine a frequency of the fractional-N PLL output clock signal.

19. A programmable jitter attenuator, comprising:

a controlled oscillator with an oscillator control code (OCC) input, and an output configured to produce an output clock signal;

a counter with an input coupled with the controlled oscillator output, wherein the counter may include a modulo-K counter;

a programmable processor with a first input coupled with a counter output, a second input configured for receiving a primary reference clock signal, a third input configured for receiving a secondary reference signal, and an output coupled with the controlled oscillator input to provide an OCC;

a tangible non-transitory memory coupled with the programmable processor and configured to store at least one of program instructions or data;

wherein the programmable processor is programmed to execute instructions for the following operations;

(a) based on a primary reference clock signal and a rational primary frequency control word (FCW), calculating an integer primary predicted phase;

based on the primary reference clock signal and the output clock signal, sampling a phase at the counter output to obtain an integer primary sampled phase;

calculating a primary difference by subtracting the primary sampled phase from the primary predicted phase;

(b) loop filtering the primary difference in a primary loop filter to obtain a secondary FCW;

(c) based on the secondary FCW and the secondary reference clock signal, calculating a secondary predicted phase;

based on the secondary reference clock signal and the output clock signal, sampling a phase to obtain a secondary sampled phase;

calculating a secondary difference by subtracting the secondary sampled phase from the secondary predicted phase;

(d) loop filtering the secondary difference in a secondary loop filter to obtain the OCC to control a frequency of the output clock signal; and

(e) forwarding the OCC to the OCC input.

20. The programmable jitter attenuator of claim 19, wherein the OCC is digital.

21. The programmable jitter attenuator of claim 19, wherein the OCC is analog, the programmable jitter attenuator further comprising a digital-to-analog converter to convert a digital OCC provided by the programmable processor to analog.

22. A tangible non-transitory memory, carrying software instructions for the following operations:

(a) in a programmable processor, based on a primary reference clock signal and a rational primary frequency control word (FCW), calculating an integer primary predicted phase;

based on a primary reference clock signal and a controlled oscillator output clock signal, sampling a phase at a counter output to obtain an integer primary sampled phase, wherein the counter may include a modulo-K counter;

calculating a primary difference by subtracting the primary sampled phase from the primary predicted phase;

(b) filtering the primary difference in a primary loop filter to obtain a secondary FCW;

(c) based on the secondary FCW and a secondary reference clock signal, calculating a secondary predicted phase;

based on the secondary reference clock signal and the output clock signal, sampling a phase to obtain a secondary sampled phase;

calculating a secondary difference by subtracting the secondary sampled phase from the secondary predicted phase;

(d) filtering the secondary difference in a secondary loop filter to obtain an oscillator control code (OCC) to control a frequency of the output clock signal; and

(e) forwarding the OCC to a controlled oscillator input.