SEMICONDUCTOR CELL CONFIGURED TO PERFORM LOGIC OPERATIONS

• US 20180144240A1
• Filed: 11/21/2017
• Published: 05/24/2018
• Est. Priority Date: 11/21/2016
• Status: Abandoned Application

• Current Assignee: IMEC International, Katholieke Universiteit Leuven
• Original Assignee: IMEC International, Katholieke Universiteit Leuven
• Inventors: Garbin, Daniele, Rodopoulos, Dimitrios, Debacker, Peter, Raghavan, Praveen
• Application Number:
  US15/820,239
• Publication Number:
  US 20180144240A1
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H03K 19/168 using thin-film devices

Abstract

The disclosed technology generally relates to machine learning, and more particularly to integration of basic machine learning kernels in a semiconductor device. In an aspect, a semiconductor cell is configured to perform one or more logic operations such as one or both of an XNOR and an XOR operation. The semiconductor cell includes a memory unit configured to store a first operand, an input port unit configured to receive a second operand and a switch unit configured to implement one or more logic operations on the stored first operand and the received second operand. The semiconductor cell additionally includes a readout port configured to provide an output of one or more logic operations. A plurality of cells may be organized in an array, and one or more of such arrays may be used to implement a neural network.

Claims

1. A semiconductor cell configured to perform one or more logic operations comprising one or both of a logic XNOR operation and a logic XOR operation, the semiconductor cell comprising:

a memory unit configured to store a first operand;

an input port unit configured to receive a second operand;

a switch unit configured to implement one or more logic operations comprising one or both of the logic XNOR operation and the logic XOR operation on the stored first operand and the received second operand; and

a readout port configured to provide an output of the one or more logic operations.

2. The semiconductor cell according to claim 1, wherein the switch unit is configured to be provided with both the stored first operand and a complement of the stored first operand, and further provided with the received second operand and a complement of the received second operand, to perform the one or more logic operations.

3. The semiconductor cell according to claim 2, wherein the memory unit comprises a first memory element configured to store the first operand and a second memory element configured to store the complement of the first operand.

4. The semiconductor cell according to claim 2, wherein the switching unit comprises:

a first switch electrically connected to the first memory element and configured to be controlled by the received second operand; and

a second switch electrically connected to the second memory element and configured to be controlled by the complement of the received second operand,

wherein the stored first operand is switchably connected through the first switch, and the complement of the stored first operand is switchably connected through the second switch, to a common node that is coupled to the readout port.

5. The semiconductor cell according to claim 1, wherein the memory unit is a non-volatile memory unit.

6. The semiconductor cell according to claim 5, wherein the non-volatile memory unit comprises one or more non-volatile memory elements configured to support multi-level readout.

7. The semiconductor cell according to claim 6, wherein the switch unit is implemented using vertical transistors comprising a channel extending in a direction perpendicular to a main surface of a substrate.

8. An array of cells logically organized in rows and columns, wherein each of the cells is a semiconductor cell according to claim 7.

9. The array according to claim 8, wherein the rows and the columns comprise word lines and read bit lines, wherein the word lines are configured to deliver second operands to input ports of the semiconductor cells, and wherein the read bit lines are configured to receive outputs of the one or both of the logic XNOR operation and the logic XOR operation from readout ports of the cells in the array connected to the read bit lines.

10. The array according to claim 8, further comprising a sensing unit shared between different cells of the array.

11. The array according to claim 8, further comprising a pre-processing unit configured to generate the second operand for at least one of the semiconductor cells in the array.

12. The array according to claim 8, configured such that the readout port of at least one semiconductor cell from at least one row and at least one column of the array is read by at least one sensing unit configured to distinguish between at least two levels of a readout signal at the readout port of the at least one semiconductor cell.

13. The array according to claim 12, further comprising at least one post-processing unit configured to implement at least one logical operation on at least one value read out of the array.

14. The array according to claim 9, further comprising allocation units for allocating subsets of the array to nodes of a directed graph.

15. A set comprising a plurality of arrays, each of the arrays according to claim 8, wherein the arrays are connected to one another in a directed graph.

16. The set according to claim 15, wherein the arrays are statically connected according to a directed graph.

17. The set according to claim 15, further comprising intermediate routing units for reconfiguring connectivity between the arrays.

18. A 3-dimensional-array comprising at least two arrays each according to claim 8, wherein the semiconductor cells of respective arrays are physically stacked in layers including one of the layers on top of another one of the layers.

19. A method of using at least one array of semiconductor cells according to claim 8 for implementation in a neural network, the method comprising:

storing layer weights as the first operands of each of the semiconductor cells; and

providing layer activations as the second operands of each of the semiconductor cells.

20. The method according to claim 19, for implementation in a multi-layer perceptrons (MLPs), wherein the first operands are weights that interconnect two MLP layers and the second operands are input-dependent activations.

21. The method according to claim 19, for implementation in a convolutional neural networks (CNNs), wherein the first operands are filters that are convolved with the second operands that are input-dependent activations.

22. The method according to claim 19, wherein the at least one array of semiconductor cells is used, for the implementation in the neural network, as arrays of semiconductor cells in at least an input layer, an output layer, and at least one intermediate layer, the method further comprising performing algebraic operations to values of the at least one intermediate layer of the implemented NN.

23. A method of operating a neural network, implemented by at least one array of semiconductor cells according to claim 8, wherein operating the neural network is performed in a clocked regime, and wherein the XNOR or XOR operation within a semiconductor cell of the at least one array is completed within one or more clock cycles.