SEMICONDUCTOR CELL CONFIGURED TO PERFORM LOGIC OPERATIONS
First Claim
1. A semiconductor cell configured to perform one or more logic operations comprising one or both of a logic XNOR operation and a logic XOR operation, the semiconductor cell comprising:
- a memory unit configured to store a first operand;
an input port unit configured to receive a second operand;
a switch unit configured to implement one or more logic operations comprising one or both of the logic XNOR operation and the logic XOR operation on the stored first operand and the received second operand; and
a readout port configured to provide an output of the one or more logic operations.
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Accused Products
Abstract
The disclosed technology generally relates to machine learning, and more particularly to integration of basic machine learning kernels in a semiconductor device. In an aspect, a semiconductor cell is configured to perform one or more logic operations such as one or both of an XNOR and an XOR operation. The semiconductor cell includes a memory unit configured to store a first operand, an input port unit configured to receive a second operand and a switch unit configured to implement one or more logic operations on the stored first operand and the received second operand. The semiconductor cell additionally includes a readout port configured to provide an output of one or more logic operations. A plurality of cells may be organized in an array, and one or more of such arrays may be used to implement a neural network.
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Citations
23 Claims
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1. A semiconductor cell configured to perform one or more logic operations comprising one or both of a logic XNOR operation and a logic XOR operation, the semiconductor cell comprising:
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a memory unit configured to store a first operand; an input port unit configured to receive a second operand; a switch unit configured to implement one or more logic operations comprising one or both of the logic XNOR operation and the logic XOR operation on the stored first operand and the received second operand; and a readout port configured to provide an output of the one or more logic operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification