DISPLAY DEVICE AND CONTROL METHOD THEREOF

• US 20180144700A1
• Filed: 07/12/2016
• Published: 05/24/2018
• Est. Priority Date: 05/26/2016
• Status: Active Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: ZENG, Dekang
• Granted Patent: US 10,276,114 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

A display device and a control method thereof are provided. The display device includes a source module and an array module. The source module includes a receiving unit receiving the image signal and extracting a control signal and a pixel signal from the image signal, a clock signal generating unit generating a plurality of clock signals, wherein periods of each clock signal of the plurality of clock signal are the same and high level periods of each clock signal do not overlap with each other, a level boosting unit boosting a voltage of the extracted control signal and pixel signal to the analog operating voltage, and a digital-to-analog conversion unit converting the voltage of the boosted pixel signal into the grayscale voltage. The array module includes a shift register outputting the pixel signal having the grayscale voltage based on the boosted control signal and the generated plurality of clock signals.

Claims

1. A display device, wherein the display device includes a source module and an array module, wherein the source module includes:

a receiving unit receiving an image signal and extracting a control signal and a pixel signal from the image signal;

a clock signal generating unit generating a plurality of clock signals, wherein periods of each clock signal of the plurality of clock signals are the same and high level periods of each clock signal do not overlap with each other;

a level boosting unit boosting a voltage of the extracted control signal and pixel signal to the analog operating voltage; and

a digital-to-analog conversion unit converting the voltage of the boosted pixel signal into the grayscale voltage,

the array module includes;

a shift register outputting the pixel signal having the grayscale voltage based on the boosted control signal and the generated plurality of clock signals.

2. The display device according to claim 1, wherein the array module further include an amplifying circuit amplifying a voltage of the pixel signal having the grayscale voltage outputted by the shift register to display the image.

3. The display device according to claim 1, wherein the number of the plurality of clock signal is greater than or equal to 3.

4. The display device according to claim 1, wherein the control signal is obtained based on the line start signal in the image signal.

5. The display device according to claim 1, wherein when the control signal and the first clock signal of the plurality of clock signals are converted into the high level, the shift register successively outputs the corresponding pixel signals during a high level of each clock signal of the plurality of clock signals.

6. The display device according to claim 1, wherein the level boosting unit and the digital-to-analog conversion unit use two channels which are respectively positive and negative.

7. A method of controlling a display device, wherein the display device includes a source module and an array module, the method includes:

the source module receives an image signal and extracting a control signal and a pixel signal from the image signal;

the source module generates a plurality of clock signals, wherein periods of each clock signal of the plurality of clock signals are the same and high level periods of the each clock signal do not overlap with each other;

the source module boosts a voltage of the extracted control signal and pixel signal to the analog operating voltage;

the source module converts the voltage of the boosted pixel signal into the grayscale voltage; and

the array module outputs the pixel signal having the grayscale voltage based on the boosted control signal and the generated plurality of clock signals.

8. The method according to claim 7, wherein the number of a plurality of clock signal is greater than or equal to 3.

9. The method according to claim 7, wherein the array module amplifies a voltage of the output pixel signal having the grayscale voltage to display the image.

10. The method according to claim 7, wherein the source module obtains the control signal based on the line start signal in the image signal,

wherein the step that the array module outputs the pixel signal having the grayscale voltage includes:

when the control signal and the first clock signal of the plurality of clock signals are converted into the high level, the array module successively outputs the corresponding pixel signals during a high level of each clock signal of the plurality of clock signals.