METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED CIRCUIT PACKAGE

• US 20180144963A1
• Filed: 11/23/2016
• Published: 05/24/2018
• Est. Priority Date: 11/23/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Refai-Ahmed, Gamal, Ramalingam, Suresh, Mardi, Mohsen H., Lee, Tien-Yu, Barber, Ivor G., Chang, Cheang-Whang, Gandhi, Jaspreet Singh
• Granted Patent: US 10,096,502 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/67109 mainly by convection
• CPC Class Codes: H01L 21/67333 Trays for chips magazine for components H05K13/0084
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/75252 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

Claims

1. A clamping assembly tray for packaging a semiconductor device, comprising:

a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and

a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

2. The clamping assembly tray of claim 1, wherein the compressible member comprises a plurality of springs.

3. The clamping assembly tray of claim 2, wherein each of the plurality of springs is formed of metal.

4. The clamping assembly tray of claim 3, wherein each of the plurality of springs is bonded to the bottom surface of the frame using a weld or solder.

5. The clamping assembly tray of claim 1, wherein the compressible member comprises a plurality of elastic objects.

6. The clamping assembly tray of claim 1, wherein the compressible member comprises an elastic material.

7. The clamping assembly tray of claim 1, further comprising:

a heating element disposed in the frame beneath the bottom surface.

8. An apparatus for assembling an integrated circuit (IC) package, comprising:

a frame having a bottom surface and side walls extending from the bottom surface that define a cavity;

a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface, the support surface being between the bottom surface and a top edge of the side walls;

a semiconductor device disposed on the support surface within the cavity; and

a lid disposed on the semiconductor device.

9. The apparatus of claim 8, wherein the semiconductor device comprises a substrate and a plurality of integrated circuit (IC) dies mounted to the substrate.

10. The apparatus of claim 9, further comprising:

thermal interface material disposed between the plurality of IC dies and the lid.

11. The apparatus of claim 8, further comprising:

a weight disposed on top of the lid.

12. The apparatus of claim 8, further comprising:

a heating element disposed in the frame beneath the bottom surface.

13. The apparatus of claim 8, wherein the substrate includes a curved surface and wherein the support surface of the compressible members conforms to the curved surface of the substrate.

14. The apparatus of claim 8, further comprising:

a weight assembly disposed on top of the lid, the weight assembly including;

a top member;

a plurality of weights; and

another plurality of compressible members disposed between the top member and the plurality of weights, each of the other plurality of compressible members attached to the top member and to one of the plurality of weights.

15. The apparatus of claim 14, wherein the weight assembly further comprises a plurality of elongate members integral with the top member and disposed between the plurality of weights.

17. The apparatus of claim 8, wherein the compressible member comprises plurality of springs.

18. The apparatus of claim 8, wherein the compressible member comprises a plurality of elastic objects.

19. The apparatus claim 8, wherein the compressible member comprises an elastic material.

20. A method of assembly a plurality of integrated circuit (IC) packages, comprising:

forming a plurality of semiconductor devices each having a plurality of IC dies mounted to a substrate;

placing the semiconductor devices on a compressible member in cavities of a clamping assembly tray;

depositing thermal interface material on plurality of IC dies of each of the plurality of semiconductor devices;

placing a lid on each of the semiconductor devices; and

heating the semiconductor devices while applying pressure to the lids to form the plurality of IC packages.