HIGH-MOBILITY SEMICONDUCTOR SOURCE/DRAIN SPACER

• US 20180145077A1
• Filed: 06/26/2015
• Published: 05/24/2018
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: DEWEY, Gilbert, METZ, Matthew V., MURTHY, Anand S., GHANI, Tahir, RACHMADY, Willy, MOHAPATRA, Chandra S., KAVALIEROS, Jack T., GLASS, Glenn A.
• Granted Patent: US 10,211,208 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

Claims

1-22. -22. (canceled)

23. A transistor, comprising:

a fin comprising a first semiconductor material;

a gate stack over a lateral channel region of the first semiconductor material; and

a source and a drain comprising a second semiconductor material, the source and the drain each laterally spaced apart from the gate stack by a gate sidewall spacer, and each vertically spaced apart from the lateral channel region by a thickness of semiconductor material that has a lower impurity concentration than the second semiconductor material.

24. The transistor of claim 23, wherein:

the source and drain are vertically spaced apart from the lateral channel region by a thickness of the first semiconductor material; and

the first semiconductor material has a carrier mobility greater than that of silicon.

25. The transistor of claim 24, wherein:

a first height of the fin from an underlying substrate at a location beyond the gate sidewall spacer is greater than a second height of the fin within the lateral channel region; and

a first width of the fin beyond the gate sidewall spacer is greater than a second width of the fin within the lateral channel region.

26. The transistor of claim 25, wherein the first width of the fin is greater than the second width of the fin by twice the difference between the first and second heights.

27. The transistor of claim 23, wherein:

the first semiconductor material comprises is first III-V compound semiconductor material and the fin is over a sub-fin comprising a second III-V compound semiconductor;

the source and drain further comprise a third III-V compound semiconductor material in contact with the first III-V compound semiconductor material; and

the third III-V compound semiconductor is separated from the second III-V compound semiconductor material by the first III-V compound semiconductor material.

28. The transistor of claim 23, wherein:

the fin is over a substrate comprising silicon; and

the first semiconductor material is an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb.

29. The transistor of claim 28, wherein:

the first semiconductor material comprises a first III-V compound semiconductor material and the fin is on a sub-fin comprising a second III-V compound semiconductor is an alloy of AlSb, an alloy of GaSb, an alloy of GaAlSb, and alloy of GaAsSb, an alloy of InAlAs, an alloy of GaAs, or and alloy of AlGaAs.

30. The transistor of claim 23, wherein:

the thickness of the semiconductor material vertically spacing the source/drain regions apart from the lateral channel region has the same impurity dopant concentration as the lateral channel region;

the gate sidewall spacer comprises a gate insulator of the gate stack; and

the gate sidewall spacer separates a sidewall of a metal gate electrode of the gate stack from a top surface of the semiconductor material vertically spacing the source and drain apart from the lateral channel region.

31. A CMOS integrated circuit (IC), comprising:

a silicon substrate;

an n-type III-V-channeled fin field effect transistor (FET) over a first region of the substrate, the III-V finFET further including;

a fin of a first III-V compound semiconductor material;

a metal-insulator gate stack and a gate stack sidewall spacer over a lateral channel region of the first III-V compound semiconductor material; and

a source and drain comprising a second semiconductor material, the source and drain each laterally spaced apart from the gate stack by a gate sidewall spacer, the source and drain vertically spaced apart from the lateral channel region by a thickness of semiconductor material having a lower impurity concentration than the second semiconductor material; and

a p-type silicon-channeled finFET over a second region of the substrate.

32. The CMOS IC of claim 31, wherein:

the source and drain are each vertically spaced apart from the lateral channel region by a thickness of the first semiconductor material;

the first semiconductor has a carrier mobility greater than that of silicon;

a first height of the fin from the substrate at a location beyond the gate sidewall spacer is greater than a second height of the fin within the lateral channel region;

a first width of the fin beyond the gate sidewall spacer is greater than a second width of the fin within the lateral channel region; and

the p-type finFET comprises a fin of a width equal to the second width.

33. The CMOS IC of claim 31, wherein:

a gate length associated with the n-type finFET is less than a corresponding gate length associated with the p-type finFET; and

a difference between the effective channel length and the gate length of the n-type finFET is greater than that of an effective channel length of the p-type finFET.

34. The CMOS IC of claim 33, wherein a substrate area occupied by the n-type finFET is smaller than that occupied by the p-type finFET.

35. The CMOS IC of claim 31, wherein:

the first semiconductor material comprises an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb; and

the fin is on a sub-fin of a second III-V compound semiconductor material comprising an alloy of AlSb, an alloy of GaSb, an alloy of GaAlSb, an alloy of GaAsSb, an alloy of InAlAs, an alloy of GaAs, or an alloy of AlGaAs.

36. A method of fabricating a high carrier mobility fin field effect transistor (FET), the method comprising:

forming a fin over a substrate, the fin comprising a monocrystalline semiconductor material different than that of the substrate;

masking a lateral channel region of the fin;

epitaxially growing a spacer comprising a semiconductor material at ends of the fin beyond the masked lateral channel region; and

forming a source and a drain at the ends of the fin, the source and the drain comprising an impurity dopant at a concentration that is higher than within the spacer.

37. The method of claim 36, further comprising forming a gate stack over the lateral channel region, and forming contact metallization to the source and drain.

38. The method of claim 36, wherein epitaxially growing the spacer further comprises growing, over the fin, an additional thickness of the semiconductor material present within the lateral channel region.

39. The method of claim 36, wherein epitaxially growing the spacer further comprises:

recess etching the fin semiconductor material not covered by the mask; and

epitaxially growing a monocrystalline layer of the spacer semiconductor material along monocrystalline sidewall surfaces of the recessed fin semiconductor material.

40. The method of claim 39, wherein epitaxially growing the spacer semiconductor material further comprises growing a III-V compound semiconductor material having the same composition as the recessed fin semiconductor material.

41. The method of claim 39, wherein:

recess etching the fin semiconductor material exposes a surface of a sub-fin located below the fin, the sub-fin further comprising a second semiconductor material; and

epitaxially growing the layer of the spacer semiconductor material further comprises growing the spacer semiconductor material on the exposed surface of the second semiconductor material, and on a sidewall surface of the fin semiconductor material.

42. The method of claim 36, wherein forming the mask over the lateral channel region further comprises:

depositing a sacrificial gate stack;

patterning the sacrificial gate stack into a stripe extending over the lateral channel region; and

forming a lateral spacer adjacent to sidewalls of the stripe, the lateral spacer comprising a dielectric material.

43. The method of claim 37, wherein forming the gate stack over the lateral channel region further comprises:

recess etching the fin semiconductor within the lateral channel region after removing the mask;

depositing a high-k gate dielectric material over recessed fin semiconductor within the lateral channel region; and

depositing a gate metal over the high-k gate dielectric.

44. The method of claim 36, wherein:

forming the fin further comprises forming a fin comprising an alloy of InGaAs, an alloy of InAs, an alloy of InP, or an alloy of InSb.