STACKED FIELD-EFFECT TRANSISTOR SWITCH
First Claim
1. A stacked field-effect transistor (FET) switch comprising:
- a first FET device stack that is operable in an on-state and in an off-state, the first FET device stack comprising a first plurality of FET devices coupled in series between a first port and a second port and having a conductance that decreases with increasing voltage between the first port and the second port between 10% and 99% of a first breakdown voltage of the first FET device stack; and
a second FET device stack that is operable in the on-state and in the off-state, the second FET device stack comprising a second plurality of FET devices coupled in series between the first port and the second port and having a conductance that increases with increasing voltage between the first port and the second port between 10% and 99% of a second breakdown voltage of the second FET device stack.
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Accused Products
Abstract
A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.
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Citations
21 Claims
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1. A stacked field-effect transistor (FET) switch comprising:
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a first FET device stack that is operable in an on-state and in an off-state, the first FET device stack comprising a first plurality of FET devices coupled in series between a first port and a second port and having a conductance that decreases with increasing voltage between the first port and the second port between 10% and 99% of a first breakdown voltage of the first FET device stack; and a second FET device stack that is operable in the on-state and in the off-state, the second FET device stack comprising a second plurality of FET devices coupled in series between the first port and the second port and having a conductance that increases with increasing voltage between the first port and the second port between 10% and 99% of a second breakdown voltage of the second FET device stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification