Phase Locked Loops Having Decoupled Integral and Proportional Paths
First Claim
Patent Images
1. A circuit, comprising:
- a phase detector configured to generate a control signal based on a comparison of a phase of a reference signal to a phase of a feedback signal;
a first charge pump configured to generate a first current at a first node in response to the control signal;
a second charge pump configured to generate a second current at a second node in response to the control signal;
an isolation buffer coupled between the first node and the second node;
an adder having a first input coupled to the second node;
an auxiliary charge pump configured to generate a third current at a second input of the adder in response to a second control signal;
an oscillator having an input coupled to an output of the adder, wherein the oscillator is configured to generate an output signal based on the output of the adder;
a frequency divider circuit having an input coupled to an output of the oscillator, wherein the frequency divider circuit is configured to generate the feedback signal based on the output signal, wherein a ratio of a frequency of the output signal to a frequency of the reference signal comprises an integer portion of a divide ratio and a fractional portion of the divide ratio;
a first fractional control module configured to provide a first factor to the frequency divider circuit, the first factor comprising the fractional portion of the divide ratio and quantization noise;
an integrating circuit having an input coupled to an output of the first fractional control mode, the integrating circuit being configured to generate a phase signal based on the quantization noise; and
a second fractional control module having an input coupled to an output of the integrating circuit, the second fractional control module being configured to generate the second control signal based on the phase signal.
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Abstract
An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.
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Citations
21 Claims
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1. A circuit, comprising:
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a phase detector configured to generate a control signal based on a comparison of a phase of a reference signal to a phase of a feedback signal; a first charge pump configured to generate a first current at a first node in response to the control signal; a second charge pump configured to generate a second current at a second node in response to the control signal; an isolation buffer coupled between the first node and the second node; an adder having a first input coupled to the second node; an auxiliary charge pump configured to generate a third current at a second input of the adder in response to a second control signal; an oscillator having an input coupled to an output of the adder, wherein the oscillator is configured to generate an output signal based on the output of the adder; a frequency divider circuit having an input coupled to an output of the oscillator, wherein the frequency divider circuit is configured to generate the feedback signal based on the output signal, wherein a ratio of a frequency of the output signal to a frequency of the reference signal comprises an integer portion of a divide ratio and a fractional portion of the divide ratio; a first fractional control module configured to provide a first factor to the frequency divider circuit, the first factor comprising the fractional portion of the divide ratio and quantization noise; an integrating circuit having an input coupled to an output of the first fractional control mode, the integrating circuit being configured to generate a phase signal based on the quantization noise; and a second fractional control module having an input coupled to an output of the integrating circuit, the second fractional control module being configured to generate the second control signal based on the phase signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 21)
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9. A phase locked loop, comprising:
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a phase detector configured to generate a control signal based on a comparison of a phase of a reference signal to a phase of a feedback signal; a first charge pump coupled to the phase detector and configured to receive the control signal from the phase detector; a second charge pump coupled to the phase detector and configured to receive the control signal from the phase detector; a filter coupled between the first charge pump and the second charge pump, a first terminal of the filter coupled to an output of the first charge pump at a first node, a second terminal of the filter coupled to an output of the second charge pump at a second node; an adder having a first terminal coupled to the second node; an auxiliary charge pump having an output coupled to a second terminal of the adder; an oscillator having an input coupled to an output of the adder; and a fractional control module configured to provide a second control signal to the auxiliary charge pump. - View Dependent Claims (10, 11, 12, 13)
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14. (canceled)
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15. A method, comprising:
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generating a feedback signal based on a first control signal comprising an integer portion, a fractional portion, and a quantization noise component; comparing the feedback signal with a reference signal; generating a first current at a first node based on the comparison of the feedback signal with the reference signal; generating a second current at a second node based on the comparison of the feedback signal with the reference signal, the second current being greater than the first current; filtering the first current using a first filter path; filtering the second current using a second filter path different from the first filter path, the second filter path decoupled from the first filter path by an isolating buffer coupled between the first filter path and the second filter path; generating a second control signal based on the quantization noise component of the first control signal; generating a third current based on the second control signal; subtracting the third current from the second current to produce a tuning voltage; and generating an oscillating signal based on the tuning voltage. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification