ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL

• US 20180149934A1
• Filed: 05/23/2016
• Published: 05/31/2018
• Est. Priority Date: 04/05/2016
• Status: Abandoned Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: WANG, Meng
• Application Number:
  US15/124,365
• Publication Number:
  US 20180149934A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/086 UV absorbing
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/124 interdigital
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An array substrate and a liquid crystal display panel are provided. The array substrate includes a base substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a first insulating layer, and a third metal layer. The active layer is used for forming a channel. The second metal layer includes a drain region and a source region of the thin film transistor. The third metal layer includes a light protection region. The position of the light protection region corresponds to the position of the channel.

Claims

1. An array substrate, comprising:

a base substrate;

a first metal layer disposed on the base substrate and including a gate region of a thin film transistor;

a gate insulating layer disposed on the first metal layer for separating the first metal layer from a second metal layer;

an active layer, a part of which is disposed on the gate insulating layer for forming a channel;

an ohmic contact layer disposed on the active layer;

the second metal layer disposed on the ohmic contact layer and including a drain region and a source region of the thin film transistor;

a first insulating layer disposed on the second metal layer; and

a third metal layer disposed on the first insulating layer and including a light protection region, wherein a position of the light protection region corresponds to a position of the channel, and an area of the light protection region projected on the base substrate is slightly larger an area of the channel projected on the base substrate.

2. The array substrate as claimed in claim 1, wherein the third metal layer further includes a pixel electrode, and the light protection region and the pixel electrode are obtained in a processing step.

3. The array substrate as claimed in claim 1, further comprising a transparent conductive layer disposed on the third metal layer and including a pixel electrode.

4. The array substrate as claimed in claim 1, further comprising a flat layer disposed on the third metal layer.

5. The array substrate as claimed in claim 1, wherein a material of the ohmic contact layer is silicon nitride.

6. An array substrate, comprising:

a base substrate;

a first metal layer disposed on the base substrate and including a gate region of a thin film transistor;

a gate insulating layer disposed on the first metal layer for separating the first metal layer from a second metal layer;

an active layer, a part of which is disposed on the gate insulating layer for forming a channel;

the second metal layer disposed on the active layer and including a drain region and a source region of the thin film transistor;

a first insulating layer disposed on the second metal layer; and

a third metal layer disposed on the first insulating layer and including a light protection region, wherein a position of the light protection region corresponds to a position of the channel.

7. The array substrate as claimed in claim 6, wherein the third metal layer further includes a pixel electrode, and the light protection region and the pixel electrode are obtained in a processing step.

8. The array substrate as claimed in claim 6, further comprising a transparent conductive layer disposed on the third metal layer and including a pixel electrode.

9. The array substrate as claimed in claim 6, wherein an area of the light protection region projected on the base substrate is slightly larger than an area of the channel projected on the base substrate

10. The array substrate as claimed in claim 6, further comprising a flat layer disposed on the third metal layer.

11. The array substrate as claimed in claim 6, further comprising an ohmic contact layer disposed between the active layer and the second metal layer.

12. The array substrate as claimed in claim 11, wherein a material of the ohmic contact layer is silicon nitride.

13. A liquid crystal display panel, comprising:

a color filter substrate disposed opposite an array substrate;

a liquid crystal layer disposed between the color filter substrate and the array substrate, and the array substrate including;

a base substrate;

a first metal layer disposed on the base substrate and including a gate region of a thin film transistor;

a gate insulating layer disposed on the first metal layer for separating the first metal layer from a second metal layer;

an active layer, a part of which is disposed on the gate insulating layer for forming a channel;

the second metal layer disposed on the active layer and including a drain region and a source region of the thin film transistor;

a first insulating layer disposed on the second metal layer; and

a third metal layer disposed on the first insulating layer and including a light protection region, wherein a position of the light protection region corresponds to a position of the channel.

14. The liquid crystal display panel as claimed in claim 13, wherein the third metal layer further includes a pixel electrode, and the light protection region and the pixel electrode are obtained in a processing step.

15. The liquid crystal display panel as claimed in claim 13, further comprising a transparent conductive layer disposed on the third metal layer and including a pixel electrode.

16. The liquid crystal display panel as claimed in claim 13, wherein an area of the light protection region projected on the base substrate is slightly larger than an area of the channel projected on the base substrate

17. The liquid crystal display panel as claimed in claim 13, further comprising a flat layer disposed on the third metal layer.

18. The liquid crystal display panel as claimed in claim 13, further comprising an ohmic contact layer disposed between the active layer and the second metal layer.

19. The liquid crystal display panel as claimed in claim 18, wherein a material of the ohmic contact layer is silicon nitride.