SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20180151501A1
• Filed: 03/15/2017
• Published: 05/31/2018
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YU, CHEN-HUA, WU, KAI-CHIANG, LU, CHUN-LIN
• Granted Patent: US 10,529,666 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias

Abstract

A semiconductor structure includes a first die; a first molding encapsulating the first die; a second die disposed over the first molding, and including a first surface, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface; and a second molding disposed over the first molding and surrounding the second die, wherein the first surface of the second die faces the first molding, and the second die is at least partially covered by the second molding.

Claims

1. A semiconductor structure, comprising:

a first die 101;

a first molding 102 encapsulating the first die;

a second die 103-1 or 103-3 disposed over the first molding, and including a first surface 103a-1/103a-3, a second surface 103b-1/103b-3 opposite to the first surface, and a sidewall 103c-1 between the first surface and the second surface; and

a second molding 104 disposed over the first molding and surrounding the second die,

wherein the first surface of the second die faces the first molding, and the second die 103-1 or 103-3 is at least partially covered by the second molding 104.

2. The semiconductor structure of claim 1, wherein the sidewall of the second die is partially 103c-1 or entirely 103c-3 covered by the second molding 104.

3. The semiconductor structure of claim 1, wherein the second surface 103b-1 of the second die 103-1 is at a level higher than a level of a top surface of the second molding 104.

4. The semiconductor structure of claim 1, wherein the second surface 103b-3 of the second die 103-3 is partially covered by the second molding.

5. The semiconductor structure of claim 4, wherein the second surface 103b-3 of the second die 103-3 is at a level lower than a level of a top surface of the second molding 104.

6. The semiconductor structure of claim 1, further comprising a third die 103-3 disposed adjacent to the second die 103-1 and encapsulated by the second molding.

7. The semiconductor structure of claim 1, further comprising a third die 103-1 disposed adjacent to the second die 103-3 and at least partially covered by the second molding.

8. The semiconductor structure of claim 6, wherein a thickness of the third die 103-3 is less than a thickness of the second die 103-1.

9. The semiconductor structure of claim 6, wherein a top surface 104a of the second molding 104 is at a level higher than a level of a surface of the third die 103-3.

10. The semiconductor structure of claim 1, further comprising a dielectric layer 105 disposed between the first molding 102 and the second die 103-1 or 103-3, and an interconnect structure 106 disposed within the dielectric layer to electrically connect the second die with the first die.

11. The semiconductor structure of claim 1, further comprising a conductive via 110 extending through the first molding 102.

12. A semiconductor structure, comprising:

a first die 101;

a first molding 102 encapsulating the first die;

a second die 103-2 disposed over the first molding 102 and including a first surface 103a-2, a second surface 103b-2 opposite to the first surface, and a sidewall 103c-2 between the first surface and the second surface; and

a second molding 104 disposed over the first molding and surrounding the second die,

wherein the first surface 103a-2 faces the first molding, the second molding includes a recess 104b-2, the second die 103-2 is disposed within the recess 104b-2, and the second surface 103b-2 and the sidewall 103c-2 of the second die 103-2 are apart from the second molding 104.

13. The semiconductor structure of claim 12, wherein the second surface 103b-2 and the sidewall 103c-2 of the second die 103-2 are entirely exposed.

14. The semiconductor structure of claim 12, wherein a width of the recess 104b-2 is greater than a width of the second die 103-2.

15. The semiconductor structure of claim 12, further comprising a dielectric layer 105 disposed between the first molding 102 and the second die 103-2 and an interconnect structure 106 disposed within the dielectric layer, the recess being disposed over a portion of the interconnect structure.

16. The semiconductor structure of claim 15, wherein the second die 103-2 is disposed over the portion of the interconnect structure.

21. The semiconductor structure of claim 12, further comprising a third die 103-1 or 103-3 disposed adjacent to the second die, and a sidewall of the third die is at least partially covered by the second molding.

17-20. -20. (canceled)

22. A semiconductor structure, comprising:

a first die 103-1;

a second die 103-2 adjacent to the first die;

a third die 103-3 adjacent to the first die; and

a molding 104,

wherein the first die, the second die and the third die are molded in the molding with different mold coverage.

23. The semiconductor structure of claim 22, wherein a sidewall 103c-1 of the first die 103-1 is partially covered by the molding.

24. The semiconductor structure of claim 22, wherein a sidewall 103c-2 of the second die 103-2 is entirely exposed through the molding.

25. The semiconductor structure of claim 22, wherein a sidewall 103c-3 of the third die 103-3 is entirely covered by the molding.