SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

• US 20180151573A1
• Filed: 11/22/2017
• Published: 05/31/2018
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: LI, Yong
• Granted Patent: US 10,199,382 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.

Claims

1. A method for fabricating a semiconductor device, comprising:

providing a base substrate including an N-type logic region, a P-type logic region, a first pull down (PD) transistor region, a second PD transistor region, and a pass gate (PG) transistor region, wherein the N-type logic region includes a first N-type threshold-voltage (TV) region used to form a first N-type device and a second N-type TV region used to form a second N-type device, the P-type logic region includes a first P-type TV region used to form a first P-type device and a second P-type TV region used to form a second P-type device;

forming a gate dielectric layer on a portion of the base substrate in the N-type logic region, the P-type logic region, the first PD transistor region, the second PD transistor region, and the PG transistor region;

forming a first work function (WF) layer on the gate dielectric layer in the first N-type TV region, the P-type logic region, the second PD transistor region, and the PG transistor region;

forming a second WF layer on the first WF layer in the first P-type TV region;

forming a third WF layer on the second WF layer in the first P-type TV region, the first WF layer in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PD transistor region, wherein a thickness of the third WF layer is smaller than a thickness of the first WF layer; and

forming a fourth WF layer on the third WF layer in the P-type logic region, the second N-type TV region, and the first PD transistor region, and on the first WF layer in the first N-type TV region, the second PD transistor region, and the PG transistor region.

2. The method for fabricating the semiconductor device according to claim 1, wherein:

a threshold voltage of the first N-type device is larger than a threshold voltage of the second N-type device; and

a threshold voltage of the first P-type device is smaller than a threshold voltage of the second P-type device.

3. The method for fabricating the semiconductor device according to claim 1, wherein

forming the first WF layer, the second WF layer and the third WF layer includes:

forming the first WF layer on the gate dielectric layer;

forming the second WF layer on the first WF layer;

removing a portion of the second WF layer in the second P-type TV region, the second N-type TV region, and the first PD transistor region;

removing a portion of the first WF layer in the second N-type TV region and the first PD transistor region;

forming the third WF layer on a remaining portion of the second WF layer, the first WF layer in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PD transistor region; and

removing a portion of the third WF layer and the second WF layer in the first N-type TV region, the second PD transistor region, and the PG transistor region.

4. The method for fabricating the semiconductor device according to claim 3, wherein

forming the first WF layer on the gate dielectric layer includes:

forming a first WF material layer on the gate dielectric layer; and

forming a second WF material layer on the first WF material layer, wherein;

the second WF material layer and the first WF material layer together form the first WF layer,

the first WF material layer and the second WF layer are made of a same material, and

the second WF material layer and the second WF layer are made of different materials.

5. The method for fabricating the semiconductor device according to claim 4, wherein:

the first WF material layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the second WF material layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the second WF layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the third WF layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN; and

the fourth WF layer is made of at least one of TiAl, TiAlC, TaAl, TaAlC, TiAlN, TaCN, and AlN.

6. The method for fabricating the semiconductor device according to claim 3, wherein:

the first WF material layer, the second WF layer, and the third WF layer are made of TiN;

the second WF material layer is made of TaN;

the thickness of the first WF layer is in a range of approximately 10 Å

to 40 Å

;

a thickness of the second WF layer is in a range of approximately 5 Å

to 30 Å

;

the thickness of the third WF layer is in a range of approximately 5 Å

to 20 Å

; and

a thickness of the fourth WF layer is in a range of approximately 40 Å

to 60 Å

.

7. The method for fabricating the semiconductor device according to claim 3, wherein removing the portion of the second WF layer in the second P-type TV region, the second N-type TV region, and the first PD transistor region as well as the portion of the first WF layer in the second N-type VT region and the first PD transistor region includes:

removing the second WF layer in the second P-type TV region; and

removing both the second WF layer and the first WF layer in the second N-type TV region and the first PD transistor region.

8. The method for fabricating the semiconductor device according to claim 1, after forming the gate dielectric layer and prior to forming the first WF layer, further including:

forming a cap layer on the gate dielectric layer; and

forming an etch stop layer on the cap layer, wherein;

the cap layer is made of TiN or TiSiN, and

the etch stop layer is made of TaN or TaSiN.

9. The method for fabricating the semiconductor device according to claim 1, wherein:

the PG transistor region includes a first PG transistor region used to form a first PG transistor and a second PG transistor region used to form a second PG transistor.

10. The method for fabricating the semiconductor device according to claim 1, wherein:

the base substrate also includes a pull up (PU) transistor region;

the gate dielectric layer is formed in the PU transistor region, the first WF layer is formed on the gate dielectric layer in the PU transistor region, and the third WF layer is formed on the first WF layer in the PU transistor region;

the first WF layer in the PU transistor region is formed simultaneously with the first WF layer in the second P-type TV region; and

the third WF layer in the PU transistor region is formed simultaneously with the third WF layer in the second P-type TV region.

11. The method for fabricating the semiconductor device according to claim 1, wherein the second N-type TV region includes an N-type ultra-low threshold-voltage (ULTV) region and an N-type low threshold-voltage (LTV) region, the first N-type TV region is an N-type standard TV region, the first P-type TV region includes a P-type ULTV region and a P-type LTV region, and the second P-type TV region is a P-type standard TV region, and wherein, prior to forming the gate dielectric layer:

a first N-type TV doping adjustment process is performed on the base substrate in the N-type ULTV region;

a second N-type TV doping adjustment process is performed on the base substrate in the N-type LTV region;

a first P-type TV doping adjustment process is performed on the base substrate in the P-type ULTV region; and

a second P-type TV doping adjustment process is performed on the base substrate in the P-type LTV region.

12. The method for fabricating the semiconductor device according to claim 1, after forming the fourth WF layer, further including:

forming a gate electrode layer on the fourth WF layer.

13. The method for fabricating the semiconductor device according to claim 1, wherein:

the base substrate includes a substrate and a plurality of fin structures formed on the substrate; and

the gate dielectric layer is formed across the fin structures and covers a portion of top and sidewall surfaces of the fin structures.

14. A semiconductor device, comprising:

a base substrate including an N-type logic region, a P-type logic region, a first pull down (PD) transistor region, a second PD transistor region, and a pass gate (PG) transistor region, wherein the N-type logic region includes a first N-type threshold-voltage (TV) region used to form a first N-type device and a second N-type TV region used to form a second N-type device, the P-type logic region includes a first P-type TV region used to form a first P-type device and a second P-type TV region used to form a second P-type device;

a gate dielectric layer formed on a portion of the base substrate in the N-type logic region, the P-type logic region, the first PD transistor region, the second PD transistor region, and the PG transistor region;

a first WF layer on the gate dielectric layer in the first N-type TV region, the P-type logic region, the second PD transistor region, and the PG transistor region;

a second WF layer formed on the first WF layer in the first P-type TV region;

a third WF layer formed on the second WF layer in the first P-type TV region, the first WF layer in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PD transistor region, wherein a thickness of the third WF layer is smaller than a thickness of the first WF layer; and

a fourth WF layer formed on the third WF layer in the P-type logic region, the second N-type TV region, and the first PD transistor region, and on the first WF layer in the first N-type TV region, the second PD transistor region, and the PG transistor region.

15. The semiconductor device according to claim 14, wherein:

the first WF layer includes a first WF material layer and a second WF material layer formed on the first WF material layer;

the first WF material layer and the second WF layer are made of a same material; and

the second WF material layer and the second WF layer are made of different materials.

16. The semiconductor device according to claim 15, wherein:

the first WF material layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the second WF material layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the second WF layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN;

the third WF layer is made of at least one of Ta, TiN, TaN, TaSiN, and TiSiN; and

the fourth WF layer is made of at least one of TiAl, TiAlC, TaAl, TaAlC, TiAlN, TaCN, and AlN.

17. The semiconductor device according to claim 16, wherein:

the first WF material layer, the second WF layer, and the third WF layer are made of TiN;

the second WF material layer is made of TaN;

the thickness of the first WF layer is in a range of approximately 10 Å

to 40 Å

;

a thickness of the second WF layer is in a range of approximately 5 Å

to 30 Å

;

the thickness of the third WF layer is in a range of approximately 5 Å

to 20 Å

; and

a thickness of the fourth WF layer is in a range of approximately 40 Å

to 60 Å

.

18. The semiconductor device according to claim 14, wherein:

the base substrate also includes a PU transistor region; and

the gate dielectric layer is formed in the PU transistor region, the first WF layer is formed on the gate dielectric layer in the PU transistor region, and the third WF layer is formed on the first WF layer in the PU transistor region.

19. The semiconductor device according to claim 14, wherein:

the PG transistor region includes a first PG transistor region and a second PG transistor region; and

the first PG transistor region includes a first PG transistor and the second PG transistor region includes a second PG transistor.

20. The semiconductor device according to claim 14, further including:

a gate electrode layer formed on the fourth WF layer.