SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
First Claim
1. A method for fabricating a semiconductor structure, comprising:
- providing a base substrate having an N-type logic region including a first N-type threshold voltage region and a second N-type threshold voltage region, a P-type logic region including a first P-type threshold voltage region and a second P-type threshold voltage region, a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;
forming a gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region;
forming a first work function layer on the gate dielectric layer;
removing portions of the first work function layer in the N-type logic region, the pull-up transistor region and the second P-type threshold voltage region;
forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer;
removing a portion of the second work function layer in the second N-type threshold voltage region;
forming an N-type work function layer on remaining second work function layer and exposed portions of the gate dielectric layer in the second N-type threshold voltage region; and
forming a gate electrode layer on the N-type work function layer.
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Abstract
Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer.
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Citations
20 Claims
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1. A method for fabricating a semiconductor structure, comprising:
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providing a base substrate having an N-type logic region including a first N-type threshold voltage region and a second N-type threshold voltage region, a P-type logic region including a first P-type threshold voltage region and a second P-type threshold voltage region, a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region; forming a gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer in the N-type logic region, the pull-up transistor region and the second P-type threshold voltage region; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer in the second N-type threshold voltage region; forming an N-type work function layer on remaining second work function layer and exposed portions of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor structure, comprising:
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a base substrate, having an N-type logic region including a first N-type threshold voltage region and a second N-type threshold voltage region, a P-type logic region including a first P-type threshold voltage region and a second P-type threshold voltage region, a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region; a gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region; a first work function layer on portions of the gate dielectric layer in the first P-type threshold voltage and the pull-up transistor region; a second work function layer on a portion of the gate dielectric layer in the first N-type threshold voltage region, a portion of the gate dielectric layer in the second P-type threshold voltage region, a portion of the gate dielectric layer in the pull-down transistor region and portions of the first work function layer in the first P-type threshold voltage region and the pull-up transistor region; an N-type work function layer on the second work function layer and a portion of the gate dielectric layer in the second N-type threshold voltage region; and a gate electrode layer on the N-type work function layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification