SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

• US 20180151575A1
• Filed: 11/09/2017
• Published: 05/31/2018
• Est. Priority Date: 11/28/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: LI, Yong
• Granted Patent: US 10,199,383 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer.

Claims

1. A method for fabricating a semiconductor structure, comprising:

providing a base substrate having an N-type logic region including a first N-type threshold voltage region and a second N-type threshold voltage region, a P-type logic region including a first P-type threshold voltage region and a second P-type threshold voltage region, a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;

forming a gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region;

forming a first work function layer on the gate dielectric layer;

removing portions of the first work function layer in the N-type logic region, the pull-up transistor region and the second P-type threshold voltage region;

forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer;

removing a portion of the second work function layer in the second N-type threshold voltage region;

forming an N-type work function layer on remaining second work function layer and exposed portions of the gate dielectric layer in the second N-type threshold voltage region; and

forming a gate electrode layer on the N-type work function layer.

2. The method according to claim 1, wherein forming the second work function layer on the remaining first work function layer and the exposed portion of the gate dielectric layer and removing the portion of the second work function layer in the second N-type threshold voltage region comprise:

forming a first second-work function material layer on the remaining first work function layer and the exposed portions of the gate dielectric layer;

removing a portion of the first second-work function material layer in the second N-type threshold voltage region to expose a portion of the gate electrode layer in the N-type threshold voltage region;

forming a second second-work function material layer on remaining first second-work function material layer and a portion of the gate dielectric layer in the second N-type threshold voltage region, the remaining first second-work function material layer and the second second-work function material layer forming the second work function layer; and

removing a portion of the second second-work function material layer in the second N-type threshold voltage region.

3. The method according to claim 2, wherein:

the first work function layer, the first second-work function material layer and the second second-work function material layer are made of TiN;

a thickness of the first work function layer is in a range of approximately 15 Å

-35 Å

;

a thickness of the first second-work function material layer is in a range of approximately 10 Å

-30 Å

; and

a thickness of the second second-work function material layer is in a range of approximately 10 Å

-30 Å

.

4. The method according to claim 2, after forming the first second-work function material layer on the remaining first work function layer and the exposed portions of the gate dielectric layer and before removing the first second-work function material layer in the N-type threshold voltage, further comprising:

forming a barrier layer on the first second-work function material layer; and

removing a portion of the barrier layer in the second N-type threshold voltage region, wherein;

the second second-work function material is formed on remaining barrier layer; and

the first second-work function material layer, the barrier layer and the second second-work function material layer are used to form the second work function layer.

5. The method according to claim 4, wherein:

the barrier layer is made of one of TaN, TiSiN, and TaSiN.

6. The method according to claim 4, wherein:

a thickness of the barrier layer is in range of approximately 5 Å

-15 Å

.

7. The method according to claim 2, wherein the base structure has a transfer gate transistor region, wherein:

the gate dielectric layer is also formed on a portion of the base substrate in the transfer gate transistor region during a process for forming gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region;

the first work function layer is also formed on a portion of the gate dielectric layer in the transfer gate transistor region during a process for forming the first work function layer on the gate dielectric layer;

a portion of the first work function layer in the transfer gate transistor region is also removed during a process for removing portions of the first work function layer in the N-type logic region, the pull-down transistor region and the second P-type threshold voltage region;

the second second-work function material layer is also formed on a portion of the gate dielectric layer in the transfer gate transistor region during a process for forming the second second-work function material layer on remaining first work function layer and the portion of the gate dielectric layer in the second N-type threshold voltage region; and

the N-type work function layer is also formed on a portion of the second second-work function material layer in the transfer gate transistor region during the process for forming the N-type work function layer on remaining second work function layer and a portion of the gate dielectric layer in the second N-type threshold voltage region.

8. The method according to claim 1, wherein:

the N-type work function layer is made of TiAlC; and

the thickness of the N-type work function layer is in a range of approximately 20 Å

-80 Å

.

9. The method according to claim 1, after forming the gate dielectric layer on the portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region and before forming the first work function layer, further comprising:

performing a thermal annealing process on the base substrate.

10. The method according to claim 1, wherein:

the base substrate is used to form fin field-effect transistors;

the base substrate includes a semiconductor substrate and a plurality of fins on the semiconductor substrate; and

the dielectric layer is across the plurality of fins by covering side and top surfaces of the plurality of fins.

11. A semiconductor structure, comprising:

a base substrate, having an N-type logic region including a first N-type threshold voltage region and a second N-type threshold voltage region, a P-type logic region including a first P-type threshold voltage region and a second P-type threshold voltage region, a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;

a gate dielectric layer on portions of the base substrate in the N-type logic region, the P-type logic region, the pull-up transistor region and the pull-down transistor region;

a first work function layer on portions of the gate dielectric layer in the first P-type threshold voltage and the pull-up transistor region;

a second work function layer on a portion of the gate dielectric layer in the first N-type threshold voltage region, a portion of the gate dielectric layer in the second P-type threshold voltage region, a portion of the gate dielectric layer in the pull-down transistor region and portions of the first work function layer in the first P-type threshold voltage region and the pull-up transistor region;

an N-type work function layer on the second work function layer and a portion of the gate dielectric layer in the second N-type threshold voltage region; and

a gate electrode layer on the N-type work function layer.

12. The semiconductor structure according to claim 11, wherein:

a first N-type device is in the first N-type threshold voltage region;

a second N-type device is in the second N-type threshold voltage region;

a threshold voltage of the first N-type device is greater than a threshold voltage of the second N-type device;

a first P-type device is in the first P-type threshold voltage region;

a second P-type device is in the second P-type threshold voltage region; and

a threshold voltage of the first P-type device is smaller than a threshold voltage of the second P-type device.

13. The semiconductor structure according to claim 11, wherein the second work function layer comprises:

a first second-work function material layer on a portion of the gate dielectric layer in the first N-type threshold voltage region, a portion of the gate dielectric layer in the second P-type work function layer, a portion of the first work function layer in the first P-type work function layer and a portion of the first work function layer in the pull-up transistor region; and

a second second-work function material layer over the first second-work function material layer.

14. The semiconductor structure according to claim 13, wherein:

the first work function layer, the first second-work function material layer and the second second-work function material layer are made of TiN;

a thickness of the first work function layer is in a range of approximately 15 Å

-35 Å

;

a thickness of the first second-work function material layer is in a range of approximately 10 Å

-30 Å

; and

a thickness of the second second-work function material layer is in a range of approximately 10 Å

-30 Å

.

15. The semiconductor structure according to claim 13, wherein, the base substrate including a transfer gate transistor region, wherein:

the second second-work function material layer is also formed on a portion of the gate dielectric layer in the transfer gate transistor region; and

the N-type work function layer is also on the second second-work function material layer in the transfer gate transistor region.

16. The semiconductor structure according to claim 13, the second work function further comprising:

a barrier layer between the first second-work function material layer and the second second-work function material layer.

17. The semiconductor structure according to claim 16, wherein:

the barrier layer is made one of TaN, TiSiN, and TaSiN.

18. The semiconductor structure according to claim 16, wherein:

a thickness of the barrier layer is in a range of approximately 5 Å

-15 Å

.

19. The semiconductor structure according to claim 11, wherein:

the N-type work function layer is made of TiAlC; and

a thickness of the N-type work function layer is a range of approximately 20 Å

-80 Å

.

20. The semiconductor structure according to claim 11, wherein:

the semiconductor structure is a fin field-effect transistor structure;

the base substrate includes a semiconductor substrate and a plurality of fins on the semiconductor substrate; and

the gate dielectric layer is across the plurality of fins by covering side and top surfaces of the plurality of fins.