THREE DIMENSIONAL INTEGRATED CIRCUITS EMPLOYING THIN FILM TRANSISTORS

• US 20180151583A1
• Filed: 03/25/2016
• Published: 05/31/2018
• Est. Priority Date: 03/25/2015
• Status: Active Grant

• Current Assignee: Tacho Holdings, LLC
• Original Assignee: 3B Technologies, Inc.
• Inventors: Lupino, James John, Agan, Tommy Allen
• Granted Patent: US 10,304,846 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

An integrated circuit which enables lower cost and improved features compared to standard crystalline silicon integrated circuits by utilizing thin film transistors (TFTs) in 2D and 3D memory and logic devices, including NAND flash memory and other nonvolatile memories such as RRAM, NRAM, MRAM, FeRAM or PCRAM. By utilizing TFTs, density is improved and die area and costs are reduced. Volumetric memory arrays of several layers may be fabricated with greatly reduced area requirements for periphery circuits and routing. Under 5% area requirements are possible. Ultra-wide I/O may be implemented without die area penalty. Vertical TFTs and logic gates provide better density and high speed approaching or exceeding that of crystalline silicon.

Claims

1. A memory device comprising:

an insulative substrate;

a non-monocrystalline active-device layer deposited upon the insulative substrate, the non-monocrystalline active device layer comprising a plurality of active devices;

an insulative layer on the non-monocrystalline active-device layer; and

a three-dimensional volumetric memory array disposed on top of the insulative layer and directly above one or more to the plurality of active devices,

wherein the three-dimensional volumetric memory array is electrically connected to the non-monocrystalline active-device layer via a plurality of vias through the insulative layer and between the three-dimensional volumetric memory array and the non-monocrystalline active device layer.

2. The memory device of claim 1, wherein the plurality of active devices are electrically configured as decoder logic for the three-dimensional volumetric memory array.

3. The memory device of claim 1, wherein the plurality of active devices are electrically configured as drivers for the three-dimensional volumetric memory array.

4. The memory device of claim 1, wherein the plurality of active devices are electrically configured as sense circuitry for the three-dimensional volumetric memory array.

5. The memory device of claim 1, wherein the dielectric substrate comprises glass (plastic, etc.).

6. The memory device of claim 1, further comprising a display screen having a plurality of display pixels.

7. The memory device of claim 6, wherein the display screen is disposed above or below the three dimensional volumetric memory array.

8. The memory device of claim 1, wherein a ratio of a number of a first portion of the plurality of active devices to a number of a second portion of active devices is less than 10%, wherein the first portion of active devices are not located directly below the three-dimensional volumetric memory array, and the second portion of active devices are located directly below the three-dimensional volumetric memory array.

9. A memory device comprising:

a substrate;

a three-dimensional volumetric memory array disposed on top of the substrate; and

a non-monocrystalline active device layer disposed upon the three-dimensional volumetric memory array, the non-monocrystalline active device layer comprising a plurality of active devices, wherein the non-monocrystalline active device layer is electrically connected to the three-dimensional volumetric memory array via a plurality of vias that are located between the three-dimensional volumetric memory array and the non-monocrystalline active device layer.

10. The memory device of claim 9, wherein the plurality of active devices are electrically configured as decoder logic for the three-dimensional volumetric memory array.

11. The memory device of claim 9, wherein the plurality of active devices are electrically configured as drivers for the three-dimensional volumetric memory array.

12. The memory device of claim 9, wherein the plurality of active devices are electrically configured as sense circuitry for the three-dimensional volumetric memory array.

13. The memory device of claim 9, wherein the substrate is a monocrystalline semiconductor substrate having a plurality of active devices.

14. The memory device of claim 13, wherein the plurality of active devices are configured as a processor.

15. The memory device of claim 9, wherein the substrate is an insulative substrate.

16. The memory device of claim 9, wherein the non-monocrystalline active device layer is a first non-monocrystalline active device layer and the plurality of vias is a first plurality of vias, the memory device further comprising:

a second non-monocrystalline active device layer disposed upon the first non-monocrystalline active device layer, the second non-monocrystalline active device layer comprising a plurality of active devices, wherein the second non-monocrystalline active device layer is electrically connected to first non-monocrystalline active device layer via a second plurality of vias that are located between the second non-monocrystalline active device layer and the first non-monocrystalline active device layer.

17. A memory device comprising:

a substrate having a first plurality of active devices;

a first insulative layer on the substrate;

a non-monocrystalline active-device layer on the first insulative layer, the non-monocrystalline active-device layer having a second plurality of active devices, wherein one or more of the second plurality of active devices is in electrical communication with one or more of the first plurality of active devices via one or more vias through the first insulative layer and between the non-monocrystalline active-device layer and the substrate;

a second insulative layer on the non-monocrystalline active-device layer; and

a three-dimensional volumetric memory array disposed on top of the second insulative layer, wherein the three-dimensional volumetric memory array is electrically connected to the non-monocrystalline active-device layer via a plurality of vias through the second insulative layer and between the three-dimensional volumetric memory array and the non-monocrystalline active device layer.

18. The memory device of claim 17, wherein the substrate is a monocrystalline semiconductor substrate.

19. The memory device of claim 17, wherein the non-monocrystalline active-device layer is a second non-monocrystalline active-device layer, and wherein the substrate is an insulative substrate having a first non-monocrystalline active-device layer deposited thereupon.

20. The memory device of claim 17, wherein the three-dimensional volumetric memory array is disposed directly above one or more of the second plurality of active devices.

21. The memory device of claim 17, wherein the substrate is an insulative substrate, and wherein the first plurality of active devices comprises a third plurality of active devices.

22. The memory device of claim 17, wherein the first plurality of active devices comprise a third plurality of MOSFET transistors.

23. The memory device of claim 17, wherein the first plurality of active devices are configured as a processor.

24. The memory device of claim 17, further comprising:

a second non-monocrystalline active-device layer on the three-dimensional volumetric memory array, the second non-monocrystalline active-device layer having a third plurality of active devices.

25. A method of manufacturing a memory device, the method comprising the steps of:

providing an insulative substrate;

depositing a non-monocrystalline active device layer on the provided substrate;

selectively doping the deposited non-monocrystalline active device layer so as to form a plurality of active devices, the active devices having a minimum critical dimension;

disposing a three-dimensional volumetric memory array on top of the deposited non-monocrystalline active device layer; and

connecting the disposed three-dimensional volumetric memory array to the plurality of active devices formed in the deposited non-monocrystalline active device layer,

wherein the thermal budget of the sum of the depositing, the selectively doping, the disposing, and the connecting steps is less than 30% of the minimum critical dimension, wherein the thermal budget measured as a change in the critical dimension resulting from diffusion of carriers in response to the thermal budget.

26. A method of manufacturing a memory device, the method comprising the steps of:

providing a substrate;

disposing a three-dimensional volumetric memory array on top of the provided substrate; and

depositing a non-monocrystalline active device layer on the three-dimensional volumetric memory array;

selectively doping the deposited non-monocrystalline active device layer so as to form a plurality of active devices;

connecting one or more of the plurality of active devices to the three-dimensional volumetric memory array deposited on the substrate,

wherein the thermal budget of the sum of the disposing, the depositing, the selectively doping, and the connecting steps is less than 30% of the minimum critical dimension, wherein the thermal budget measured as a change in the critical dimension resulting from diffusion of carriers in response to the thermal budget.