THIN FILM TRANSISTOR AND DISPLAY PANEL USING THE SAME

• US 20180151650A1
• Filed: 11/28/2017
• Published: 05/31/2018
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: HA, JongMoo
• Granted Patent: US 10,211,270 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/0238 Improving the black level
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 2102/311 Flexible OLED
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance
• CPC Class Codes: H10K 59/86 Series electrical configurations of multiple OLEDs
• CPC Class Codes: H10K 77/111 : Flexible substrates

Abstract

Provided is a display panel to which a dual gate transistor is applied. The display panel includes a substrate including a pixel area and a non-pixel area and a dual gate transistor disposed on the non-pixel area. The dual gate transistor includes first and second transistors which are connected in series and an auxiliary electrode which connects two gate electrodes of the first and second transistors. The auxiliary electrode is on a layer which is different from the gate electrode. Therefore, an area in which the dual gate transistor is formed is reduced and stability of the driving circuit is secured.

Claims

1. A display panel, comprising:

a substrate including a pixel area and a non-pixel area; and

a dual gate transistor on the non-pixel area,

wherein the dual gate transistor includes first and second transistors which are connected in series, and an auxiliary electrode which connects two gate electrodes of the first and second transistors, and the auxiliary electrode is on a different layer from the gate electrode.

2. The display panel according to claim 1, wherein the dual gate transistor includes:

an active layer on the substrate,

the two gate electrodes which are on the active layer to be spaced apart from each other; and

an insulating layer disposed on the two gate electrodes connected through a contact hole in the insulating layer.

3. The display panel according to claim 2, wherein the dual gate transistor includes a source electrode and a drain electrode on the insulating layer, and

the source electrode, the drain electrode, and the auxiliary electrode are formed of the same material.

4. The display panel according to claim 1, wherein the auxiliary electrode is within an area where the active layer is disposed.

5. The display panel according to claim 1, wherein the active layer is formed of polycrystalline silicon.

6. The display panel according to claim 1, wherein the dual gate transistor constitutes a gate driver disposed in the non-pixel area.

7. The display panel according to claim 1, further comprising:

a third gate transistor in which one transistor is further connected to the dual gate transistor in series.

8. A display panel, comprising:

a flexible substrate; and

a plurality of transistors on the flexible substrate,

wherein the plurality of transistors include a multiple gate transistor in which at least two transistors are connected in series, and the multiple gate transistor has a plurality of gate electrodes connected to each other through a contact hole in an insulating layer disposed on the gate electrodes.

9. The display panel according to claim 8, wherein the number of contact holes is equal to or larger than the number of the multiple gate transistor.

10. The display panel according to claim 8, further comprising an auxiliary electrode on the insulating layer.

11. The display panel according to claim 10, wherein the auxiliary electrode is in contact with the gate electrode through the contact hole.

12. The display panel according to claim 10, wherein the auxiliary electrode overlaps the gate electrode and is disposed in an area where the gate electrode is formed.

13. The display panel according to claim 8, wherein the multiple gate transistor includes a top-gate structure.

14. The display panel according to claim 13, wherein the multiple gate transistor includes an active layer formed of polycrystalline silicon.

15. A thin film transistor, comprising:

an active layer on a substrate and having two channel layers which are spaced apart from each other;

a first insulating layer on the active layer;

two gate electrodes which are spaced apart from each other on the first insulating layer to form a dual gate structure; and

a source electrode and a drain electrode which are on the active layer with the active layer therebetween and are electrically connected to the active layer through a contact hole in the first insulating layer,

wherein the two gate electrodes are electrically connected to each other through a connection structure disposed on a different layer from the two gate electrodes.

16. The thin film transistor according to claim 15, further comprising:

a second insulating layer on the first insulating layer,

wherein the connection structure is on the second insulating layer to electrically connect two gate electrodes through a contact hole in the second insulating layer.

17. The thin film transistor according to claim 16, wherein the thin film transistors connected through the connection structure have a smaller area than that of a thin film transistor having a dual gate structure in which two gate electrodes are electrically connected to each other on the same layer.

18. The thin film transistor according to claim 15, wherein the connection structure is on the same layer as the source electrode and the drain electrode.

19. The thin film transistor according to claim 15, wherein the connection structure is disposed within an area where the active layer is formed.

20. The thin film transistor according to claim 15, wherein the active layer is formed of polycrystalline silicon.