THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

• US 20180151672A1
• Filed: 10/03/2017
• Published: 05/31/2018
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Bongyong Lee
• Inventors: CHOI, Moorym, LEE, Bongyong, LIM, Junhee
• Granted Patent: US 10,403,719 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

Claims

1. A three-dimensional semiconductor memory device, comprising:

common source regions spaced apart from each other in a substrate and extending in a first direction;

an electrode structure between the common source regions adjacent to each other and extending in the first direction, the electrode structure including electrodes vertically stacked on the substrate;

first channel structures penetrating the electrode structure and including a first semiconductor pattern and a first vertical insulation layer; and

second channel structures between the first channel structures adjacent to each other and penetrating the electrode structure, the second channel structures including a second semiconductor pattern and a second vertical insulation layer, wherein the second vertical insulation layer surrounds the second semiconductor pattern and extends between the substrate and a bottom surface of the second semiconductor pattern, and wherein the second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

2. The device as claimed in claim 1, wherein:

the first channel structures are spaced apart from the common source regions by a first horizontal distance, and

the second channel structures are spaced apart from the common source regions by a second horizontal distance greater than the first horizontal distance.

3. The device as claimed in claim 1, further comprising:

a dummy impurity layer between the common source regions adjacent to each other and extending in the first direction, wherein the second channel structures are on the dummy impurity layer.

4. The device as claimed in claim 3, wherein a portion of the second vertical insulation layer is between the dummy impurity layer and the bottom surface of the second semiconductor pattern.

5. The device as claimed in claim 1, further comprising:

first and second string selection electrodes extending in the first direction and horizontally spaced apart from each other on the electrode structure, wherein the first channel structures vertically extend to penetrate the first and second string selection electrodes, and wherein the second channel structures vertically extend between the first and second string selection electrodes.

6. The device as claimed in claim 1, wherein upper widths of the first channel structures and upper widths of the second channel structures are equal.

7. The device as claimed in claim 1, further comprising:

lower semiconductor patterns,

wherein each of the lower semiconductor patterns is between the substrate and one of the first channel structures, and wherein the first vertical insulation layer and the first semiconductor pattern are in contact with the lower semiconductor pattern.

8. A three-dimensional semiconductor memory device, comprising:

first impurity layers extending in a first direction and spaced apart from each other, the first impurity layers including first impurities;

a second impurity layer extending in the first direction between the first impurity layers adjacent to each other, the second impurity layer including second impurities different from the first impurities;

an electrode structure between the first impurity layers adjacent to each other and covering the second impurity layer, the electrode structure including a plurality of electrodes vertically stacked on a substrate;

first channel structures on the substrate between the first impurity layers and penetrating the electrode structure; and

second channel structures on the second impurity layer and penetrating the electrode structure.

9. The device as claimed in claim 8, wherein each of the first channel structures includes:

a lower semiconductor pattern penetrating a lower portion of the electrode structure and in contact with the substrate;

an upper semiconductor pattern penetrating an upper portion of the electrode structure and in contact with the lower semiconductor pattern; and

a first vertical insulation layer surrounding the upper semiconductor pattern on the lower semiconductor pattern.

10. The device as claimed in claim 8, wherein:

each of the second channel structures includes a second vertical insulation layer surrounding a second semiconductor pattern,

the second vertical insulation layer extends between a second dummy impurity layer and a bottom surface of the second semiconductor pattern.

11. The device as claimed in claim 10, wherein:

each of the second channel structures includes a dummy semiconductor pattern on the second impurity layer,

a portion of the second vertical insulation layer extends between the dummy semiconductor pattern and the bottom surface of the second semiconductor pattern.

12. The device as claimed in claim 8, wherein:

the first channel structures are spaced apart from the first impurity layers by a first horizontal distance, and

the second channel structures are spaced apart from the first impurity layers by a second horizontal distance greater than the first horizontal distance.

13. The device as claimed in claim 8, further comprising:

first and second string selection electrodes extending in the first direction and horizontally spaced apart from each other on the electrode structure, wherein the first channel structures vertically extend to penetrate the first and second string selection electrodes, and wherein the second channel structures vertically extend between the first and second string selection electrodes.

14. The device as claimed in claim 8, wherein:

the first channel structures are electrically connected to the substrate, and

the second channel structures are electrically separated from the substrate.

15. A three-dimensional semiconductor memory device, comprising:

common source regions spaced apart from each other in a substrate and extending in a first direction;

an electrode structure on the substrate between the common source regions adjacent to each other and including electrodes vertically stacked on the substrate;

first channel structures penetrating the electrode structure and electrically connected to the substrate; and

second channel structures between the first channel structures adjacent to each other and penetrating the electrode structure and electrically separated from the substrate.

16. The device as claimed in claim 15, wherein:

the first channel structures are spaced apart from the common source regions by a first horizontal distance, and

the second channel structures are spaced apart from the common source regions by a second horizontal distance greater than the first horizontal distance.

17. The device as claimed in claim 15, wherein each of the first channel structures includes:

a lower semiconductor pattern penetrating a lower portion of the electrode structure and in contact with the substrate;

an upper semiconductor pattern penetrating an upper portion of the electrode structure and in contact with the lower semiconductor pattern; and

a first vertical insulation layer surrounding the upper semiconductor pattern on the lower semiconductor pattern.

18. The device as claimed in claim 17, wherein each of the second channel structures includes:

a second semiconductor pattern penetrating the electrode structure; and

a second vertical insulation layer surrounding the second semiconductor pattern and extending onto a bottom surface of the second semiconductor pattern.

19. The device as claimed in claim 18, wherein the first vertical insulation layer has a bottom surface higher than a bottom surface of the second vertical insulation layer.

20. The device as claimed in claim 18, wherein:

each of the second channel structures includes a dummy semiconductor pattern in contact with the substrate,

a portion of the second vertical insulation layer is between the dummy semiconductor pattern and the bottom surface of the second semiconductor pattern.

21-27. -27. (canceled)