SOI POWER LDMOS DEVICE

• US 20180151725A1
• Filed: 01/08/2018
• Published: 05/31/2018
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: LEE, Zachary K.
• Granted Patent: US 10,840,372 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An LDMOS device includes a handle portion having a buried dielectric layer and a semiconductor layer thereon doped a second dopant type. A drift region doped a first type is within the semiconductor layer providing a drain extension. A gate stack includes a gate electrode on a gate dielectric layer on respective sides of a junction with the drift region. A DWELL region is within the semiconductor layer. A source region doped the first type is within the DWELL region. A drain region doped the first type is within the drift region. A first partial buried layer doped the second type is in a first portion of the drift region including under the gate electrode. A second partial buried layer doped the first type is in a second portion of the drift region including under the drain.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS) device, comprising:

a handle portion having a blanket buried dielectric (BOX) layer thereon and a semiconductor layer on said BOX layer, said semiconductor layer doped a second dopant type;

a drift region doped a first dopant type within said semiconductor layer to provide a drain extension region;

a gate stack including a gate dielectric layer and a patterned gate electrode on said gate dielectric layer, said gate dielectric layer being located over a channel portion of said semiconductor layer adjacent to and on respective sides of a junction with said drift region;

a DWELL region within said semiconductor layer;

a source region doped said first dopant type within said DWELL region;

a drain region doped said first dopant type within said drift region;

a first partial buried layer doped said second dopant type in a first portion of said semiconductor layer including under at least a portion of said gate electrode, and

a second partial buried layer doped said first dopant type in a second portion of said semiconductor layer including under said drain region.

2. The LDMOS device of claim 1, further comprising a body region doped said second dopant type within said semiconductor layer, wherein said drift region and said DWELL region are formed with said body region.

3. The LDMOS device of claim 1, wherein said first partial buried layer is a blanket layer and said second partial buried layer is a localized layer having a doping level sufficiently high to counterdope a doping level in said first partial buried layer.

4. The LDMOS device of claim 1, wherein said second partial buried layer is a blanket layer and said first partial buried layer is a localized layer having a doping level sufficiently high to counterdope a doping level in said second partial buried layer.

5. The LDMOS device of claim 1, further comprising a plurality of field plates (FPs) in a staggered FP arrangement selected from said gate electrode and at least one metal layer, wherein said staggered FP arrangement comprises said FPs being staggered relative to one another with each said FP overlapping a larger portion of said drift region as its vertical distance to said drift region increases.

6. The LDMOS device of claim 1, wherein said LDMOS device comprises an NLDMOS device.

7. The LDMOS device of claim 1, wherein said LDMOS device comprises a PLDMOS device.

8. The LDMOS device of claim 1, wherein said substrate comprises silicon, wherein said gate dielectric layer comprises silicon oxide or silicon oxynitride (SiON) and wherein said gate electrode comprises polysilicon.

9. The LDMOS device of claim 1, wherein said LDMOS device comprises a first LDMOS device and a second LDMOS device, said first LDMOS device having a different said partial buried layer compared to said second LDMOS device.

10-18. -18:

(canceled)

19. An electronic device, comprising:

a substrate having a semiconductor layer thereover;

a doped buried layer within said semiconductor layer, said doped buried layer having a first buried layer region doped a first conductivity type and an adjacent second buried layer region doped a second conductivity type;

a drain region and a source region located within said semiconductor layer and having said first conductivity type;

a drift region, doped said first conductivity type, and located between said first buried layer region and said drain region and between said source region and said drain region.

20. The device of claim 19, further comprising a body region doped said second dopant type in direct contact with said first buried layer region and located between said drift region and said first buried layer region, and.

21. The device of claim 20, wherein said body region is in direct contact with said second buried layer region.

22. The device of claim 19, wherein said buried region is located directly on a buried oxide layer.

23. The device of claim 19, further comprising a gate stack located adjacent said drain region and including a gate dielectric layer located directly on said drift region and on said body region.

24. The device of claim 23, wherein said gate stack is a first gate stack, and said drain region is located between said first gate stack and a second gate stack including a second gate dielectric layer located directly on said drift region and on said body region.

25. The device of claim 23, wherein said gate stack is located over said second buried layer region.

26. The device of claim 23, further comprising a first field plate (FP) located over said gate stack and a second FP located between said first FP and said gate stack, wherein said first FP extends laterally over said substrate past an and of said second FP.

27. The device of claim 19, further comprising a source region within said substrate, wherein a portion of said body region and a portion of said drift region are located between said source region and said drain region.

28. The device of claim 19, wherein said second buried layer region comprises a blanket layer of said second conductivity type, and said first buried layer region comprises a portion of said blanket layer counterdoped to said first conductivity type.

29. The device of claim 19, wherein said first conductivity type is N-type and said second conductivity type is P-type.