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SOI POWER LDMOS DEVICE

  • US 20180151725A1
  • Filed: 01/08/2018
  • Published: 05/31/2018
  • Est. Priority Date: 01/28/2016
  • Status: Active Grant
First Claim
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1. A laterally diffused metal oxide semiconductor (LDMOS) device, comprising:

  • a handle portion having a blanket buried dielectric (BOX) layer thereon and a semiconductor layer on said BOX layer, said semiconductor layer doped a second dopant type;

    a drift region doped a first dopant type within said semiconductor layer to provide a drain extension region;

    a gate stack including a gate dielectric layer and a patterned gate electrode on said gate dielectric layer, said gate dielectric layer being located over a channel portion of said semiconductor layer adjacent to and on respective sides of a junction with said drift region;

    a DWELL region within said semiconductor layer;

    a source region doped said first dopant type within said DWELL region;

    a drain region doped said first dopant type within said drift region;

    a first partial buried layer doped said second dopant type in a first portion of said semiconductor layer including under at least a portion of said gate electrode, anda second partial buried layer doped said first dopant type in a second portion of said semiconductor layer including under said drain region.

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