SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20180151745A1
• Filed: 03/31/2017
• Published: 05/31/2018
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHANG, Chia-Wen, LIN, Hong-Nien, LEE, Chien-Hsing, CHANG, Chih-Sheng, YEH, Ling-Yen, TSAI, Wilman, YEO, Yee-Chia
• Granted Patent: US 10,937,783 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Claims

1. A semiconductor device, comprising:

a first channel region disposed over a substrate; and

a first gate structure disposed over the first channel region, wherein;

the first gate structure includes;

a gate dielectric layer disposed over the channel region;

a lower conductive gate layer disposed over the gate dielectric layer;

a ferroelectric material layer disposed over the lower conductive gate layer; and

an upper conductive gate layer disposed over the ferroelectric material layer, and

the ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

2. The semiconductor device of claim 1, wherein:

the lower conductive gate layer includes;

a work function adjustment material (WFM) layer disposed on the gate dielectric layer; and

a first conductive layer disposed over the WFM layer, and

the WFM layer has a U-shape cross section.

3. The semiconductor device of claim 2, wherein the first conductive layer does not have a U-shape cross section.

4. The semiconductor device of claim 2, wherein:

the WFM layer includes one or more layers of Ti, TiN, TiAl, TiAlC, TaN, TaAlC, Al, TiC, Co, HfTi, TiSi and TaSi, and

the first conductive layer is one or more layers of W, Co, Ni and Cu.

5. The semiconductor device of claim 1, wherein:

the lower conductive gate layer includes a work function adjustment material (WFM) layer disposed on the gate dielectric layer, and

the lower conductive layer includes none of W, Co, Ni or Cu.

6. The semiconductor device of claim 1, wherein:

the upper conductive gate layer includes;

a conductive liner layer disposed on the ferroelectric layer; and

a second conductive layer disposed over the conductive liner layer, and

the conductive liner layer has a U-shape cross section.

7. The semiconductor device of claim 6, wherein the second conductive layer does not have a U-shape cross section.

8. The semiconductor device of claim 6, wherein:

the conductive liner layer includes one or more layers of Ti, TiN, Ta and TaN, and

the second conductive layer includes one or more layers of W, Co, Ni and Cu.

9. The semiconductor device of claim 1, wherein the ferroelectric material layer includes one or more layers of Pb₃Ge₅O₁₁ (PGO), lead zirconate titanate (PZT), SrBi₂Ta₂O₉ (SBT or SBTO), SrB₄O₇ (SBO), Sr_aBi_bTa_cNb_dO_x (SBTN), SrTiO₃ (STO), BaTiO₃ (BTO), (Bi_xLa_y)Ti₃O₁₂ (BLT), LaNiO₃ (LNO), YMnO₃, ZrO₂, zirconium silicate, ZrAlSiO, HfO₂, HfZrO₂, hafnium silicate, HfAlO, LaAlO, lanthanum oxide, HfO₂ doped with Si (HfSiO_x), and Ta₂O₅.

10. The semiconductor device of claim 1, wherein:

the first gate structure further includes a gate cap insulating layer disposed over the upper conductive gate layer, and

a bottom of the gate cap insulating layer is substantially flat.

11. The semiconductor device of claim 1, wherein the first channel region is an upper portion of a first fin structure extending in a first direction.

12. A semiconductor device, comprising:

a first field effect transistor (FET); and

a second FET, wherein;

a gate structure of the first FET includes;

a first gate dielectric layer made of a dielectric material;

a first conductive layer made of a first conductive material;

a second conductive layer made of a second conductive material; and

a first gate cap insulating layer disposed on the second conductive layer,

a gate structure of the second FET includes;

a second gate dielectric layer made of the dielectric material;

a third conductive layer made of the first conductive material;

a ferroelectric material layer disposed over the second gate dielectric layer and the third conductive layer;

a fourth conductive layer disposed over the ferroelectric material layer; and

a second gate cap insulating layer disposed on the fourth conductive layer.

13. The semiconductor device of claim 12, wherein the ferroelectric material layer is in direct contact with the second gate dielectric layer and the third conductive layer, and has a U-shape cross section.

14. The semiconductor device of claim 12, wherein:

the gate structure of the second FET further includes a fifth conductive layer disposed over the third conductive layer and the ferroelectric layer, and

the first conductive layer and the third conductive layer has a U-shape cross section, respectively.

15. The semiconductor device of claim 12, wherein:

the first conductive layer has a U-shape cross section, and

the third conductive layer does not have a U-shape cross section and an entire upper surface of the third conductive layer is in contact with the ferroelectric layer.

16. The semiconductor device of claim 12, wherein:

the fourth conductive layer includes;

a conductive liner layer disposed on the ferroelectric layer; and

an upper conductive layer disposed over the conductive liner layer, and

the conductive liner layer has a U-shape cross section.

17. The semiconductor device of claim 16, wherein the upper conductive layer does not have a U-shape cross section.

18. The semiconductor device of claim 12, wherein a bottom of the second gate cap insulating layer is substantially flat.

19-20. -20. (canceled)

21. A semiconductor device, comprising:

a first channel region disposed over a substrate; and

a first gate structure disposed over the first channel region, wherein;

the first gate structure includes;

a gate dielectric layer disposed over the channel region;

a lower conductive gate layer disposed over the gate dielectric layer;

a ferroelectric material layer disposed over the lower conductive gate layer; and

an upper conductive gate layer disposed over the ferroelectric material layer,

the ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section, and

a thickness of the ferroelectric material layer above the lower conductive gate layer is in a range from 2 nm to 20 nm.

22. The semiconductor device of claim 21, wherein the ferroelectric material layer is one selected from the group consisting of HfO₂, HfZrO₂, and HfSiO_x.