Thin Film Transistor, Array Substrate and Methods for Manufacturing and Driving the same and Display Device

• US 20180151749A1
• Filed: 05/30/2016
• Published: 05/31/2018
• Est. Priority Date: 03/14/2016
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Zhang, Miao, Sun, Jing
• Application Number:
  US15/531,111
• Publication Number:
  US 20180151749A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a thin film transistor, an array substrate and method for manufacturing and driving the same, and a display device. The thin film transistor comprises an active layer formed by an oxide semiconductor material; a gate electrode insulated from the active layer; a source electrode in contact with the active layer; and a drain electrode in contact with the active layer, wherein the gate electrode comprises a first gate electrode below the active layer and a second gate electrode above the active layer.

Claims

1. A thin film transistor comprising

an active layer formed by an oxide semiconductor material;

a gate electrode insulated from the active layer;

a source electrode in contact with the active layer; and

a drain electrode in contact with the active layer;

wherein the gate electrode comprises a first gate electrode below the active layer and a second gate electrode above the active layer.

2. The thin film transistor according to claim 1, wherein the first gate electrode is directly below the active layer, and the second gate electrode is directly above the active layer.

3. The thin film transistor according to claim 1, wherein the oxide semiconductor material comprises indium gallium zinc oxide.

4. An array substrate comprising the thin film transistor according to claim 1.

5. The array substrate according to claim 4, further comprising

a first gate line electrically connected with the first gate electrode and a second gate line electrically connected with the second gate electrode;

a gate insulation layer for insulating the first gate electrode from the active layer;

a passivation layer for insulating the active layer from the second gate electrode; and

a transparent and electrically conductive layer above the passivation layer and serving as a common electrode layer or a pixel electrode layer.

6. The array substrate according to claim 5, wherein the second gate electrode is made of the same material and disposed in the same layer as the transparent and electrically conductive layer.

7. The array substrate according to claim 5, wherein the first gate electrode, the first gate line and the second gate line are made of the same material and disposed in the same layer.

8. The array substrate according to claim 5, wherein the first gate electrode, the first gate line and the second gate lines are formed on a surface of a base substrate, the gate insulation layer is above the base substrate and covers the first gate electrode, the first gate line and the second gate line, and the active layer is above the gate insulation layer.

9. The array substrate according to claim 8, further comprising an etching stop layer above the gate insulation layer and covers the active layer, wherein the source electrode and the drain electrode are in contact with the active layer through a first via hole in the etching stop layer.

10. The array substrate according to claim 9, wherein the passivation layer is above the etching stop layer and covers the source electrode and drain electrode, the second gate electrode is above the passivation layer and electrically connected with the second gate line through a second via hole passing through the passivation layer, the etching stop layer and the gate insulation layer, and the transparent and electrically conductive layer is electrically connected with the drain electrode through a third via hole in the passivation layer.

11. A display device comprising the array substrate according to claim 4.

16. A method for driving the array substrate according to claim 4, comprising:

applying a gate signal to the first gate electrode of the thin film transistor and floating the second gate electrode during displaying a n^th frame of image, wherein n is a nonzero natural number; and

applying a gate signal to the second gate electrode of the thin film transistor and floating the first gate electrode during displaying a n+1^th frame of image.

17. An array substrate comprising the thin film transistor according to claim 2.

18. An array substrate comprising the thin film transistor according to claim 3.

19. A display device comprising the array substrate according to claim 17.

20. A display device comprising the array substrate according to claim 18.

12. A method for manufacturing an array substrate comprising a thin film transistor including an active layer formed by an oxide semiconductor material, a first gate electrode and a second gate electrode insulated from the active layer, a source electrode in contact with the active layer and a drain electrode in contact with the active layer, the method comprising:

forming the first gate electrode below the active layer and forming the second gate electrode above the active layer.

13. The method according to claim 12, further comprising:

forming a first gate line electrically connected with the first gate electrode and a second gate line electrically connected with the second gate electrode on a surface of a base substrate;

forming an gate insulation layer for insulating the first gate electrode from the active layer above the base substrate, such that the gate insulation layer covers the first gate electrode, the first gate line and the second gate line, and the active layer is formed above the gate insulation layer;

forming an etching stop layer having a first via hole above the gate insulation layer such that the etching stop layer covers the active layer, and forming the source electrode and the drain electrode so that the source and drain electrodes are in contact with the active layer through the first via hole;

forming a passivation layer for insulating the active layer from the second gate electrode above the etching stop layer such that the passivation layer covers the source electrode and the drain electrode; and

forming a transparent and electrically conductive layer serving as a common electrode layer or a pixel electrode layer above the passivation layer and forming the second gate electrode above the passivation layer, such that the second gate electrode is electrically connected with the second gate line through a second via hole passing through the passivation layer, the etching stop layer and the insulation layer, and the transparent and electrically conductive layer is in contact and connected with the drain electrode through a third via hole in the passivation layer.

14. The method according to claim 13, wherein the second gate electrode and the transparent and electrically conductive layer are simultaneously formed in a single patterning process.

15. The method according to claim 13, wherein the first gate electrode, the first gate line and the second gate line are simultaneously formed in a single patterning process.