CIRCUIT, SYSTEM AND METHOD FOR THIN-FILM TRANSISTOR LOGIC GATES

• US 20180152189A1
• Filed: 05/20/2016
• Published: 05/31/2018
• Est. Priority Date: 05/20/2015
• Status: Active Grant

• Current Assignee: Manoj Sachdev, Nikolaos Papadopoulos, William S. Wong
• Original Assignee: Manoj Sachdev, Nikolaos Papadopoulos, William S. Wong
• Inventors: PAPADOPOULOS, Nikolaos, SACHDEV, Manoj, WONG, William
• Granted Patent: US 10,396,796 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/04 Maintaining the quality of display appearance
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/344 based on particles moving in a fluid or in a gas, e.g. electrophoretic devices electrophoretic devices per se G02F1/167
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence

Abstract

A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.

Claims

1. A unipolar inverter circuit for thin-film transistor circuits comprising:

a driving voltage input;

an input signal input;

a base voltage input;

a first stage comprising a first unipolar inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal received by the input signal input;

a capacitor coupled to the output of the first stage at a node A; and

a second stage comprising;

a second unipolar inverter circuit connected between the driving voltage input and the base voltage input, wherein the second unipolar inverter circuit comprises a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B rather than to the driving voltage input; and

a clamping transistor connected between the driving voltage and the node B for controlling a voltage across the capacitor, wherein the clamping transistor gate is connected to the driving voltage; and

an output provided between the second stage load transistor and the second stage driving transistor,

wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing of the output voltage at the output based on the input signal.

2. An inverter circuit according to claim 1, wherein:

the first stage comprises;

a first stage driving transistor connected to the base voltage input; and

a first stage load transistor connected to the first transistor and the driving voltage input,

wherein the first stage driving transistor gate is connected to the input signal input and the first stage load transistor gate is connected to the driving voltage input and the capacitor is connect to the node A between the first stage driving transistor and the first stage load transistor.

3. An inverter circuit according to claim 1, further comprising a switchable feedback unit configured to pull down a gate voltage of the first stage load transistor and the second stage load transistor when the input signal input is low.

4. An inverter circuit according to claim 3, wherein the switchable feedback unit comprises:

a first feedback transistor provided with a source and gate connected to the node B connecting the capacitor and the secondary load transistor and a drain connected to a node C connected to the gate of the second stage load transistor; and

a second feedback transistor provided with a source connected to the node C, a gate connected to the input signal input and a drain connected to the base voltage input,

5. An inverter circuit according to claim 4, wherein a gate of the first stage load transistor is connected to the node C instead of the driving voltage input.

6. An inverter circuit according to claim 1, wherein the driving voltage input is the only voltage input.

7. An inverter circuit according to claim 1, wherein the input signal input is the only input signal input.

8. An inverter circuit according to claim 1, wherein the transistors are a-Si:

H thin-film transistors.

9. An inverter circuit according to claim 1, wherein the transistors are transition-metal oxide transistors.

10. An inverter circuit according to claim 7, wherein the transistors are InGaZnO transistors.

11. A logic gate comprising the inverter circuit of claim 1.

12. An electronic circuit comprising the inverter circuit of claim 1.

13. A TFT display comprising the inverter circuit of claim 1.

14. A unipolar TFT inverter system comprising:

a unipolar two transistor inverter connected between a driving voltage and a base voltage;

means for boosting an output voltage of the inverter when an input signal is low; and

means for reducing a gate voltage of a load transistor of the inverter when the input signal is high.

15. A unipolar TFT inverter system according to claim 14, further comprising feedback means for reducing power consumption when the input signal is high.

16. A unipolar TFT inverter system according to claim 14, wherein the means for boosting does not require an additional voltage input.

17. A unipolar TFT inverter system according to claim 14, wherein the means for boosting does not require cross-connecting of transistors.

18. A unipolar TFT inverter system according to claim 14, wherein the means for boosting comprises boosting a gate voltage at a load transistor of the unipolar two transistor inverter.

19. A method of controlling a unipolar TFT inverter circuit, the method comprising:

boosting an output voltage when an input signal is low; and

reducing a gate voltage of a load transistor of the inverter when the input signal is high.

20. A method according to claim 19, further comprising feedback of a voltage for reducing power consumption when the input signal is high.

21. A method according to claim 19, wherein the boosting does not require an additional voltage input.