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Hybrid Phase Lock Loop

  • US 20180152192A1
  • Filed: 02/09/2017
  • Published: 05/31/2018
  • Est. Priority Date: 11/30/2016
  • Status: Active Grant
First Claim
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1. A hybrid phase lock loop (PLL), comprising:

  • a digital controlled loop configured to receive a reference input signal and an output signal of the hybrid PLL, and to generate a digital tuning word;

    an analog controlled loop configured to receive the reference input signal and the output signal of the hybrid PLL, and to generate an output voltage; and

    a hybrid oscillator coupled to the digital controlled loop and the analog controlled loop,wherein the digital controlled loop comprises an oscillator controller configured to;

    control the hybrid oscillator using the digital tuning word and disable the analog controlled loop during a frequency tracking operation mode of the hybrid PLL; and

    enable the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

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