Hybrid Phase Lock Loop
First Claim
1. A hybrid phase lock loop (PLL), comprising:
- a digital controlled loop configured to receive a reference input signal and an output signal of the hybrid PLL, and to generate a digital tuning word;
an analog controlled loop configured to receive the reference input signal and the output signal of the hybrid PLL, and to generate an output voltage; and
a hybrid oscillator coupled to the digital controlled loop and the analog controlled loop,wherein the digital controlled loop comprises an oscillator controller configured to;
control the hybrid oscillator using the digital tuning word and disable the analog controlled loop during a frequency tracking operation mode of the hybrid PLL; and
enable the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
1 Assignment
0 Petitions
Accused Products
Abstract
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
27 Citations
20 Claims
-
1. A hybrid phase lock loop (PLL), comprising:
-
a digital controlled loop configured to receive a reference input signal and an output signal of the hybrid PLL, and to generate a digital tuning word; an analog controlled loop configured to receive the reference input signal and the output signal of the hybrid PLL, and to generate an output voltage; and a hybrid oscillator coupled to the digital controlled loop and the analog controlled loop, wherein the digital controlled loop comprises an oscillator controller configured to; control the hybrid oscillator using the digital tuning word and disable the analog controlled loop during a frequency tracking operation mode of the hybrid PLL; and enable the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A hybrid PLL, comprising:
-
a digital controlled loop implemented using digital components and configured to operate during a frequency tracking mode; an analog controlled loop implemented using analog components and configured to operate during a phase tracking mode; and an oscillator controller configured to; receive an error signal; determine a trend of the error signal; compare the trend of the error signal to a previous trend of the error signal, and enable or disable the analog controlled loop upon detecting a change in the trend of the error signal. - View Dependent Claims (16, 17, 18)
-
-
19. A method for operating a hybrid phase lock loop (PLL), the method comprising:
-
during a frequency tracking operation mode of the hybrid PLL; controlling a hybrid oscillator using a digital tuning word generated by a digital controlled loop; and disabling an analog controlled loop; and during a phase tracking operation mode of the hybrid PLL; enabling the analog controlled loop to control the hybrid oscillator. - View Dependent Claims (20)
-
Specification