FILTERING COHERENCY PROTOCOL TRANSACTIONS

• US 20180157590A1
• Filed: 11/29/2017
• Published: 06/07/2018
• Est. Priority Date: 12/02/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: PERSSON, Hkan Lars-Gran, BRATT, Ian Rudolf, SWAINE, Andrew Brookfield, MATHEWSON, Bruce James
• Granted Patent: US 10,664,399 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Claims

1. A filter unit comprising:

interface circuitry to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between said first cache and at least one other cache or other master device; and

filtering circuitry to filter the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

2. The filter unit according to claim 1, wherein the filtering circuitry is configured to filter snoop transactions exchanged between the master device and the interconnect in dependence on the memory access permission data.

3. The filter unit according to claim 1, wherein the memory access permission data defines for a given region of the address space:

whether the master device is allowed to read data from the given region; and

whether the master device is allowed to write data to the given region.

4. The filter unit according to claim 1, wherein the filtering circuitry is configured to block an outgoing coherency protocol transaction issued from said master device to said interconnect, when a memory access permission violation is detected for the outgoing coherency protocol transaction in dependence on the memory access permission data.

5. The filter unit according to claim 4, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by triggering an error condition when the memory access permission violation is detected for the outgoing coherency protocol transaction.

6. The filter unit according to claim 4, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by:

returning dummy data to said master device when the outgoing coherency protocol transaction is a read transaction; and

preventing write data associated with the outgoing coherency protocol transaction being passed to said at least one other cache or other master device or a memory when the outgoing coherency protocol transaction is a write transaction.

7. The filter unit according to claim 4, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by replacing the outgoing coherency protocol transaction with an alternative coherency protocol transaction.

8. The filter unit according to claim 4, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a read transaction and the memory access permission data specifies that the master device is prohibited from reading data from a region of the address space including a target address specified by the read transaction.

9. The filter unit according to claim 4, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a write transaction and the memory access permission data specifies that the master device is prohibited from writing data to a region of the address space including a target address specified by the write transaction.

10. The filter unit according to claim 4, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is capable of causing data to be stored in said first cache in a shareable modifiable coherency state in which coherency is to be maintained between the data in said first cache and said at least one other cache or other master device and the master device is allowed to modify the data without issuing a further coherency protocol transaction to said interconnect, and the memory access permission data specifies that the master device is prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction.

11. The filter unit according to claim 4, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a transaction, other than a write transaction, which is capable of triggering invalidation of data in said at least one other cache, and the memory access permission data specifies that the master device is prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction.

12. The filter unit according to claim 4, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is capable of causing dirty data to be stored in said first cache, and the memory access permission data specifies that the master device is prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction.

13. The filter unit according to claim 1, wherein the filtering circuitry is configured to block an incoming coherency protocol transaction issued from said interconnect to said master device, when a memory access permission violation is detected for the incoming coherency protocol transaction in dependence on said memory access permission data.

14. The filter unit according to claim 13, wherein the filtering circuitry is configured to block the incoming coherency protocol transaction by preventing the incoming coherency protocol transaction being passed to said master device.

15. The filter unit according to claim 13, wherein the filtering circuitry is configured to block the incoming coherency protocol transaction by replacing the incoming coherency protocol transaction with an invalidating coherency protocol transaction for triggering invalidation from the first cache of any data associated with the target address specified by the incoming coherency protocol transaction.

16. The filter unit according to claim 13, wherein the filtering circuitry is configured to return a miss response to the interconnect in response to the blocked incoming coherency protocol transaction, the miss response indicating that a target address specified by the incoming coherency protocol transaction missed in the first cache.

17. The filter unit according to claim 13, wherein the filtering circuitry is configured to block an incoming coherency protocol transaction when the memory access permission data specifies that the master device is prohibited from reading data from a region of the address space including a target address specified by the incoming coherency protocol transaction or is prohibited from writing data to said region of the address space including said target address.

18. The filter unit according to claim 1, wherein the filtering circuitry is configured to lookup the memory access permission data in dependence on a target address of a coherency protocol transaction received from one of the master device and the interconnect, and control issuing of a coherency protocol transaction specifying said target address to the other of the master device and the interconnect in dependence on the looked up memory access permission data.

19. The filter unit according to claim 1, wherein the filtering circuitry is configured to lookup the memory access permission data in dependence on a target address of a coherency protocol transaction received from one of the master device and the interconnect, map the target address to a translated address in dependence on address translation data, and control issuing of a coherency protocol transaction specifying said translated address to the other of the master device and the interconnect in dependence on the looked up memory access permission data.

20. The filter unit according to claim 19, wherein the filtering circuitry is configured to map the target address to the translated address using a translation scheme providing a one-to-one mapping between any given target address and the corresponding translated address.

21. An apparatus comprising:

a master device comprising a first cache;

an interconnect to manage coherency between said first cache and at least one other cache or other master device using coherency protocol transactions exchanged between the master device and the interconnect; and

the filter unit according to claim 1.

22. The apparatus according to claim 21, wherein in response to a snoop transaction received from the interconnect specifying a target address for which data is currently stored in the first cache in a non-shareable coherency state, the master device is configured to return a miss indication indicating that the target address missed in said first cache.

23. The apparatus according to claim 21, wherein the master device has a predetermined coherency mode in which selected coherency transactions are prohibited, said selected coherency transactions including at least coherency transactions capable of causing data to be allocated to the first cache in a shareable state in which coherency is to be maintained between the shareable data and data at said at least one other cache or other master device;

wherein the master device is configured to switch to said predetermined coherency mode when processing protected data to be protected from access by at least one other master.

24. The apparatus according to claim 21, wherein the master device has a predetermined coherency mode in which the master device ignores incoming snoop transactions and returns a miss indication to the interconnect for said incoming snoop transactions;

wherein the master device is configured to switch to said predetermined coherency mode when processing protected data to be protected from access by at least one other master.

25. The apparatus according to claim 23, wherein the memory access permission data supports defining a given region of the address space as a read only region for which the master device is allowed to read data from the given region and is prohibited from writing data to the given region.

26. The apparatus according to claim 22, wherein the filter unit is configured to permit incoming snoop transactions received from the interconnect to be passed to the master device independent of the memory access permission data.

27. A data processing method comprising:

intercepting coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between said first cache and at least one other cache or other master device; and

filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.