MULTI-CHIP PACKAGE CAPABLE OF TESTING INTERNAL SIGNAL LINES
First Claim
1. A multi-chip package comprising:
- a printed circuit board;
a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit; and
second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines,wherein the test circuit is configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads.
1 Assignment
0 Petitions
Accused Products
Abstract
A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires.
10 Citations
20 Claims
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1. A multi-chip package comprising:
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a printed circuit board; a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit; and second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines, wherein the test circuit is configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-chip package comprising:
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a printed circuit board; a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit; and second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines, wherein the test circuit is configured to enable first and second circuits of the first semiconductor chip respectively connected to first and second pads contacting the internal signal lines of the multi-chip package, output first data to the first pad through the first circuit, receive second data from the second pad through the second circuit, and invert one of the first and second data. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A multi-chip package comprising:
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a printed circuit board; a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit, a plurality of pads, an input driver, and an output driver, the test circuit including, a write path selection circuit configured to provide first data to a first pad, from among the plurality of pads, via the output driver, a read path selection circuit configured to receive second data from a second pad, from among the plurality of pads;
via the input driver,a data inversion circuit configured to invert one of the first and second data, a first switch configured to provide the first data of the write path selection circuit to the data inversion circuit, and a second switch configured to provide the second data of the read path selection circuit to the data inversion circuit; and second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first and second pads of the first semiconductor chip via a plurality of internal signal lines. - View Dependent Claims (17, 18, 19, 20)
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Specification