DISPLAY DEVICE

• US 20180158839A1
• Filed: 11/29/2017
• Published: 06/07/2018
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: UMEZAKI, Atsushi, MIYAKE, Hiroyuki
• Granted Patent: US 10,297,618 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2320/0666 for control of colour parameters, e.g. colour temperature
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Claims

1. (canceled)

2. A display device comprising:

a pixel portion; and

a driver circuit electrically connected to the pixel portion, the driver circuit comprising;

a first transistor; and

a second transistor,

wherein one of a source and a drain of the first transistor is directly connected to a wiring,

wherein one of a source and a drain of the second transistor is directly connected to the wiring,

wherein a first clock signal is input to the other of the source and the drain of the first transistor,

wherein a second clock signal is input to a gate of the second transistor,

wherein a potential is supplied to the other of the source and the drain of the second transistor, and

wherein an output signal is output from the wiring.

3. A display device comprising:

a pixel portion; and

a driver circuit electrically connected to the pixel portion, the driver circuit comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source and a drain of the first transistor is directly connected to a wiring,

wherein one of a source and a drain of the second transistor is directly connected to the wiring,

wherein one of a source and a drain of the third transistor is directly connected to the wiring,

wherein one of a source and a drain of the fourth transistor is directly connected to a gate of the first transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the third transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the third transistor,

wherein a gate of the seventh transistor is directly connected to the gate of the first transistor,

wherein a first clock signal is input to the other of the source and the drain of the first transistor,

wherein a second clock signal is input to a gate of the second transistor,

wherein a first potential is supplied to the other of the source and the drain of the second transistor,

wherein the first potential is supplied to the other of the source and the drain of the third transistor,

wherein the first potential is supplied to the other of the source and the drain of the fourth transistor, and

wherein the first potential is supplied to the other of the source and the drain of the seventh transistor.

4. The display device according to claim 3,

wherein a start signal is input to a gate of the fifth transistor.

5. The display device according to claim 3,

wherein a reset signal is input to a gate of the sixth transistor.

6. The display device according to claim 3,

wherein an output signal is output from the wiring.

7. The display device according to claim 3,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor is an N-channel transistor,

wherein a second potential is supplied to the other of the source and the drain of the fifth transistor, and

wherein the second potential is higher than the first potential.

8. The display device according to claim 7,

wherein the first potential is supplied to the other of the source and the drain of the sixth transistor.

9. The display device according to claim 8, further comprising an eighth transistor and a ninth transistor,

wherein one of a source and a drain of the eighth transistor is directly connected to the gate of the third transistor,

wherein one of a source and a drain of the ninth transistor is directly connected to the gate of the third transistor,

wherein the second clock signal is input to a gate of the eighth transistor,

wherein a third clock signal is input to a gate of the ninth transistor,

wherein the first potential is supplied to the other of the source and the drain of the eighth transistor, and

wherein the second potential is supplied to the other of the source and the drain of the ninth transistor.

10. A display device comprising:

a pixel portion; and

a driver circuit electrically connected to the pixel portion, the driver circuit comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source and a drain of the first transistor is directly connected to a wiring,

wherein one of a source and a drain of the second transistor is directly connected to the wiring,

wherein one of a source and a drain of the third transistor is directly connected to the wiring,

wherein one of a source and a drain of the fourth transistor is directly connected to a gate of the first transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the third transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the third transistor,

wherein a gate of the seventh transistor is directly connected to the gate of the first transistor,

wherein a first clock signal is input to the other of the source and the drain of the first transistor,

wherein a second clock signal is input to a gate of the second transistor,

wherein a first potential is supplied to the other of the source and the drain of the second transistor,

wherein the first potential is supplied to the other of the source and the drain of the third transistor,

wherein the first potential is supplied to the other of the source and the drain of the fourth transistor,

wherein the first potential is supplied to the other of the source and the drain of the seventh transistor, and

wherein the gate of the third transistor is configured such that a potential of the gate of the third transistor is changed in a cycle equal to the first clock signal when the seventh transistor is in an off-state.

11. The display device according to claim 10,

wherein a start signal is input to a gate of the fifth transistor.

12. The display device according to claim 10,

wherein a reset signal is input to a gate of the sixth transistor.

13. The display device according to claim 10,

wherein an output signal is output from the wiring.

14. The display device according to claim 10,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor is an N-channel transistor,

wherein a second potential is supplied to the other of the source and the drain of the fifth transistor, and

wherein the second potential is higher than the first potential.

15. The display device according to claim 14,

wherein the first potential is supplied to the other of the source and the drain of the sixth transistor.

16. The display device according to claim 15, further comprising an eighth transistor and a ninth transistor,

wherein one of a source and a drain of the eighth transistor is directly connected to the gate of the third transistor,

wherein one of a source and a drain of the ninth transistor is directly connected to the gate of the third transistor,

wherein the second clock signal is input to a gate of the eighth transistor,

wherein a third clock signal is input to a gate of the ninth transistor,

wherein the first potential is supplied to the other of the source and the drain of the eighth transistor, and

wherein the second potential is supplied to the other of the source and the drain of the ninth transistor.