TRANSISTOR FIN FORMATION VIA CLADDING ON SACRIFICAL CORE

• US 20180158841A1
• Filed: 06/26/2015
• Published: 06/07/2018
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: GLASS, GLENN A., MURTHY, ANAND S., AUBERTINE, DANIEL B., GHANI, TAHIR, KAVALIEROS, JACK T., CHU-KUNG, BENJAMIN, MOHAPATRA, CHANDRA S., JAMBUNATHAN, KARTHIK, DEWEY, GILBERT, RACHMADY, WILLY
• Granted Patent: US 10,373,977 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

Claims

1. An integrated circuit device, comprising:

a substrate having at least one of a plurality of covered fins extending from the substrate and a plurality of covered recesses extending into the substrate, each covered fin and/or recess covered by an insulation layer; and

a fin-pair above each covered fin and/or recess, each fin-pair comprising a semiconductor material, wherein a thickness of the insulator layer separates each fin-pair from its underlying covered fin or recess.

2. The device of claim 1 wherein the covered fins comprise a material different than the substrate, and wherein the covered fins comprise at least one of silicon fins, silicon germanium fins, germanium fins, and III-V material fins.

3. The device of claim 1 wherein the covered fins comprise native fins that are part of the substrate.

4. The device of claim 1 wherein each of the fin-pairs includes two fins separated by a distance that is substantially the same as the width of the underlying covered fin or recess.

5. The device of claim 1 wherein at least some of the covered fins are silicon fins and the semiconductor material of the fin-pairs above those silicon fins comprises silicon and germanium.

6. The device of claim 1 wherein at least some of the covered fins comprise silicon and germanium and the semiconductor material of the fin-pairs above those covered fins is germanium.

7. The device of claim 1 wherein at least some of the covered fins comprise gallium and arsenic and the semiconductor material of the fin-pairs above those covered fins comprises indium, gallium, and arsenic.

8. The device of claim 1 wherein at least some of the covered fins comprise indium and phosphur and the semiconductor material of the fin-pairs above those covered fins comprises indium, gallium, and arsenic.

9. The device of claim 1 wherein at least some of the covered fins comprise gallium and antimony and the semiconductor material of the fin-pairs above those covered fins comprises indium and antimony.

10. The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise native silicon fins, and the semiconductor material of the fin-pairs above those native silicon fins comprises silicon and germanium.

11. The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise silicon and germanium fins, and the semiconductor material of the fin-pairs above those covered fins is germanium.

12. The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise III-V material fins, and the semiconductor material of the fin-pairs above those covered fins is III-V material different from the covered fin III-V material.

13. An integrated circuit device, comprising:

a substrate having a plurality of fins covered by a shallow trench isolation (STI) region;

a fin-pair above each covered fin, each fin-pair comprising a semiconductor material, wherein a thickness of insulator material of the STI region separates each fin-pair from its underlying covered fin;

a transistor gate structure on each fin of the fin-pair; and

a transistor source and a transistor drain.

14. The device of claim 13 wherein the covered fins comprise replacement fins comprising a material different than the substrate.

15. The device of claim 14 wherein the replacement fins comprise at least one of silicon fins, silicon germanium fins, germanium fins, and III-V material fins.

16. The device of claim 13 wherein the covered fins comprise native fins that are part of the substrate.

17. The device of claim 13 wherein the substrate is a bulk substrate, and each of the fin-pairs includes two fins separated by a distance that is substantially the same as the width of the underlying covered fin.

18. A method for forming a fin-based transistor structure, the method comprising:

receiving a substrate having a plurality of sacrificial fins extending from the substrate and a shallow trench isolation (STI) on opposing sides of each sacrificial fin;

recessing the STI to expose a top portion of the sacrificial fins;

forming a cladding layer of semiconductor material on the exposed portion of the sacrificial fins;

depositing insulation material to fill back in the recessed STI;

removing the sacrificial fins by etching, thereby leaving new fins made of the cladding material, and such that the new fins are separated from the sacrificial fins;

depositing further insulation material to fill back in the area left by removal of sacrificial fins;

recessing the insulation material to expose a top portion of the new fins; and

forming transistor devices using the new fins.

19. The method of claim 18 wherein depositing insulation material to fill back in the recessed STI further includes planarizing so as to remove excess insulation material, and wherein the planarizing also removes cladding on top of the sacrificial fins.

20. The method of claim 18 wherein forming transistor devices using the new fins includes at least one of a replacement metal gate (RMG) process and a replacement source/drain process.

21. to 25. (canceled)