SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS

• US 20180158859A1
• Filed: 01/19/2018
• Published: 06/07/2018
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Takahashi, Hiroshi, Sukegawa, Shunichi, Inoue, Keishi
• Granted Patent: US 10,453,886 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14632 : Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/14638 : Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/02008 : for solar cells or solar cell modules
• CPC Class Codes: H01L 31/02013 : comprising output lead wires elements
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Claims

1-13. -13. (canceled)

14. A method of manufacturing a semiconductor device including the steps of:

forming a first material layer with a first surface and a second surface;

forming a second material layer with a first surface and a second surface;

securing the second surface of the first material layer against the first surface of the second material layer; and

forming a first via and a second via simultaneously, wherein,

along a common cross section parallel to an interface between the two material layers the first via has a cross section larger than that of the second via.

15. The method of claim 14 including the steps of forming a first insulating layer in the first material layer;

and

forming a second insulating layer in the second material layer,

wherein

the first via extends into the second insulating layer in the second material layer, and the second via extends into the first insulating layer in the first material layer.

16. The method of claim 14 wherein the first via and the second via are filled with a conductive material.

17. The method of claim 15 wherein the first via reaches an second interconnect in the second insulating layer in the second material layer.

18. The method of claim 15 wherein the second via reaches a first interconnect in the first insulating layer in the first material layer.

19. The method of claim 14 including the step of forming an on chip lens over the photodiode.

20. The method of claim 14 including the step of an on chip color filter between the photodiode and the on chip lens.