ECC AND READ ADJUSTMENT BASED ON DYNAMIC MEMORY ERROR MODEL ESTIMATION

• US 20180159560A1
• Filed: 12/06/2016
• Published: 06/07/2018
• Est. Priority Date: 12/06/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: SHARON, Eran, BAZARSKY, Alexander, GOLDENBERG, Idan, ACHTENBERG, Stella, FAINZILBER, Omer, ZAMIR, Ran
• Granted Patent: US 10,158,380 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Claims

1. A device comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous, and wherein the controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

2. The device of claim 1, wherein the controller is further configured to receive, from the memory, the representation of data and reliability information associated with the representation of data, and wherein the first count and the second count are determined based on the representation of data and the reliability information.

3. The device of claim 1, wherein the at least one decode parameter comprises one or more log likelihood ratio (LLR) values, one or more soft bit values, or a combination thereof.

4. The device of claim 1, wherein the at least one read parameter comprises one or more read thresholds, one or more soft bit delta values, or a combination thereof, the one or more soft bit delta values comprising one or more voltage thresholds used to generate reliability information corresponding to the representation of the data.

5. The device of claim 1, wherein the controller is further configured to determine a third count of bits of the representation of data that have a low estimated reliability and are estimated to be correct, a fourth count of bits of the representation of data that have a low estimated reliability and are estimated to be incorrect, and a fifth count of bits of the representation of data that have a high estimated reliability and are estimated to be correct, and wherein the controller is configured to modify the at least one read parameter or the at least one decode parameter further based on the third count, the fourth count, and the fifth count.

6. The device of claim 5, wherein the controller is further configured to determine, based on the representation of data and reliability information associated with the representation of data, a bitwise syndrome vector associated with the representation of data, wherein the first count, the second count, and the third count are based on the bitwise syndrome vector and the reliability information.

7. The device of claim 1, wherein the controller is further configured to estimate an error model based at least in part on one or more count values of bits of the representation of data, wherein each count value indicates to a count of bits having a corresponding combination of bit value and number of unsatisfied parity checks, and wherein the at least one decode parameter or the at least one read parameter is modified based on the error model.

8. The device of claim 7, wherein the controller is further configured to estimate the error model based on data corresponding to a linear regression model or data corresponding to one or more bit error rate values.

9. A method performed by a controller of a device, the method comprising:

determining a first count of bits of a representation of data that are estimated to be erroneous;

determining a second count of bits of the representation of data that have a high estimated reliability and are estimated to be erroneous; and

modifying at least one read parameter or at least one decode parameter based at least on the first count and the second count.

10. The method of claim 9, further comprising initiating a read operation at a memory using the at least one modified read parameter, wherein the at least one modified read parameter comprises at least one modified read threshold, at least one modified soft bit delta value, or a combination thereof.

11. The method of claim 9, further comprising decoding the representation of the data using the modified at least one decode parameter, wherein the modified at least one decode parameter comprises at least one modified log likelihood ratio (LLR) value, at least one modified soft bit value, or a combination thereof.

12. The method of claim 9, further comprising:

determining a syndrome metric based on the representation of data, wherein the syndrome metric includes a syndrome weight or a generalized syndrome weight;

determining a count of bits of the representation of data having a particular reliability based on reliability information associated with the representation of data, wherein a bit of the representation of data has the particular reliability if a corresponding bit of the reliability information has a particular value associated with high reliability; and

modifying a second decode parameter based on the syndrome metric and the count.

13. The method of claim 9, further comprising:

determining a fourth count of bits of a second group of bits of the representation of data that are estimated to be erroneous, wherein the first count of bits and the second count of bits are associated with a first group of bits of the representation of data;

determining a fifth count of bits of the second group of bits that have a high estimated reliability and are estimated to be erroneous; and

modifying a second decode parameter based on the fourth count and the fifth count, wherein the second decode parameter is associated with the second group of bits, and wherein the at least one decode parameter is associated with the first group of bits.

14. An apparatus comprising:

means for storing data; and

means for modifying at least one read parameter or at least one decode parameter based on a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous.

15. The apparatus of claim 14, further comprising means for decoding the representation of data using the modified at least one decode parameter, wherein the modified at least one decode parameter comprises one or more log likelihood ratio (LLR) values, one or more soft bit values, or a combination thereof.

16. The apparatus of claim 14, further comprising means for reading a second representation of data from the means for storing using the modified at least one read parameter, wherein the representation of data and the second representation of data correspond to the same location at the means for storing, and wherein the modified at least one read parameter comprises one or more read thresholds, one or more soft bit delta values, or a combination thereof.

17. A device comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to determine an estimated memory error model associated with a representation of data based at least in part on the representation of data and reliability information associated with the representation of data, and wherein the controller is further configured to modify at least one read parameter or at least one decode parameter based on the estimated memory error model.

18. The device of claim 17, wherein the controller is configured to determine the estimated memory error model by computing at least two counts of bits of the representation of data that have different reliability information or by correlating the reliability information with a bitwise syndrome vector corresponding to the representation of data to determine the estimated memory error model.

19. The device of claim 17, wherein the controller is configured to determine the estimated memory error model based on joint statistics of syndrome information associated with the representation of data, the representation of data, and the reliability information.

20. The device of claim 19, wherein the estimated memory error model is associated with estimated counter values that more closely match the joint statistics than estimated counter values of other estimated memory error models, and wherein the controller is configured to determine the estimated memory error model based on a maximum likelihood analysis, a maximal a-posteriori probability analysis, or a minimum squared Euclidean distance between particular counts of bits of the representation of data and predicted counts of bits associated with the estimated memory error model.