USING NETWORK INTERFACE CONTROLLER (NIC) QUEUE DEPTH FOR POWER STATE MANAGEMENT

• US 20180164868A1
• Filed: 12/12/2016
• Published: 06/14/2018
• Est. Priority Date: 12/12/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Skerry, Brian J., Weiny, Ira, Connor, Patrick, Tai, Tsung-Yuan C., Min, Alexander W.
• Granted Patent: US 11,054,884 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/70 Virtual switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.

Claims

1. A computer-implemented method, comprising:

receiving a queue depth for a receive queue of a network interface controller (NIC);

determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth; and

responsive to a determination that the power state of the CPU core should be adjusted, adjusting the power state of the CPU core.

2. The computer-implemented method of claim 1, wherein adjusting the power state of the CPU core includes reducing the power state of the CPU core.

3. The computer-implemented method of claim 1, wherein adjusting the power state of the CPU core includes increasing the power state of the CPU core.

4. The computer-implemented method of claim 1, wherein determining whether the power state of the CPU core should be adjusted includes comparing the queue depth of the receive queue to a threshold.

5. The computer-implemented method of claim 4, wherein adjusting the power state of the CPU core includes reducing the power state of the CPU core responsive to the queue depth of the receive queue being less than the threshold.

6. The computer-implemented method of claim 4, wherein adjusting the power state of the CPU core includes increasing the power state of the CPU core responsive to the queue depth of the receive queue exceeding the threshold.

7. The computer-implemented method of claim 1, further comprising repeating the receiving and determining continuously.

8. The computer-implemented method of claim 7, further comprising repeating the receiving and determining at a specified time interval.

9. The computer-implemented method of claim 1, wherein the NIC is an Ethernet controller.

10. A system, comprising:

a network interface controller (NIC) of a first computing device, the NIC having a receive queue;

a first central processing unit (CPU) core of the first computing device, the first CPU core being mapped to the receive queue; and

hardware implementing a power algorithm to determine, based on a queue depth of the receive queue, whether a power state of the first CPU core should be adjusted.

11. The system of claim 10, wherein the power algorithm causes the power state of the first CPU core to be reduced.

12. The system of claim 10, wherein the power algorithm causes the power state of the first CPU core to be increased.

13. The system of claim 10, wherein the power algorithm compares the queue depth of the receive queue to a threshold.

14. The system of claim 13, wherein the power algorithm causes the power state of the first CPU core to be reduced responsive to a determination that the queue depth of the receive queue is less than the threshold.

15. The system of claim 13, wherein the power algorithm causes the power state of the first CPU core to be increased responsive to a determination that the queue depth of the receive queue exceeds the threshold.

16. The system of claim 10, wherein the hardware implementing the power algorithm is on the first CPU core.

17. The system of claim 10, wherein the hardware implementing the power algorithm is on a second CPU core.

18. The system of claim 17, wherein the first and second CPU cores are on different processors.

19. The system of claim 10, further comprising a power manager that includes the power algorithm.

20. The system of claim 19, wherein the power manager and the first CPU core are on different processors.

21. The system of claim 10, further comprising a second computing device for sending an incoming data packet to the first computing device.

22. The system of claim 21, wherein the receive queue receives the incoming data packet.

23. The system of claim 21, the receive queue having a receive descriptor.

24. The system of claim 23, the receive descriptor including the queue depth of the receive queue.

25. One or more non-transitory, computer-readable media comprising instructions that, when executed by a processor, cause the processor to perform a method comprising:

receiving a queue depth for a receive queue of a network interface controller (NIC);

determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth; and

responsive to a determination that the power state of the CPU core should be adjusted, adjusting the power state of the CPU core.